EE311-2009-THE2

# EE311-2009-THE2 - V t = 1 V, and k’ n (W/L) = 2 mA/V 2 ,...

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EE311 TAKE-HOME EXAM 2 (Due: 14/10/09) Q1) The figure below shows a discrete circuit CS amplifier employing the classical biasing scheme. The input signal V sig is coupled to the gate through a very large capacitor (shown as infinite). The transistor source is connected to ground at signal frequencies via a very large capacitor (shown as infinite). The output voltage signal that develops at the drain is coupled to a load resistance via a very large capacitor (shown as infinite). (a) If the transistor has
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Unformatted text preview: V t = 1 V, and k’ n (W/L) = 2 mA/V 2 , verify that the bias circuit establishes V GS = 2 V, I D = 1 mA, and V D = + 7.5 V. That is, assume these values, and verify that they are consistent with the values of the circuit components and the device parameters. (b) Find g m and r o if V A = 100 V. (c) Draw a complete small-signal equivalent circuit for the amplifier assuming all capacitors behave as short circuits at signal frequencies. (d) Find R in , v gs / v sig , v o / v gs , and v o / v sig ....
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## This note was uploaded on 05/25/2011 for the course EE 311 taught by Professor Murataskar during the Spring '11 term at Middle East Technical University.

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