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fetbias - c Copyright 2008 W Marshall Leach Jr Professor...

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c ° Copyright 2008. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The FET Bias Equation Basic Bias Equation (a) Look out of the 3 MOSFET terminals and replace the circuits with Thévenin equivalent circuits as showin in Fig. 1. Figure 1: Basic bias circuit. (b) Solve the FET drain current equation for V GS . V GS = r I D K + V TO (c) Write the gate-source loop equation in the gate-source loop and let I S = I D . V GG V SS = V GS + I S R SS = V GS + I D R SS (d) Solve the loop equation for V GS . V GS = V GG V SS I D R SS (e) Equate the two expressions for V GS and rearrange the terms to obtain a quadratic equation in I D . I D R SS + r I D K ( V GG V SS V T O ) = 0 (f) Let a = R SS , b = 1 / K , and c = ( V GG V SS V TO ) . In this case, the bias equation becomes aI D + b p I C + c = 0 Use the quadratic equation to solve for I D , then square the result to obtain I D = Ã b + b 2 4 ac 2 a !
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