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Unformatted text preview: c Copyright 2010. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical
and Computer Engineering. The MOSFET
Device Symbols
Whereas the JFET has a diode junction between the gate and the channel, the metaloxide semiconductor
FET or MOSFET diﬀers primarily in that it has an oxide insulating layer separating the gate and the
channel. The circuit symbols are shown in Fig. 1. Each device has gate (G), drain (D), and source (S)
terminals. Four of the symbols show an additional terminal called the body (B) which is not normally used
as an input or an output. It connects to the drainsource channel through a diode junction. In discrete
MOSFETs, the body lead is connected internally to the source. When this is the case, it is omitted on
the symbol as shown in four of the MOSFET symbols. In integratedcircuit MOSFETs, the body usually
connects to a dc power supply rail which reverse biases the bodychannel junction. In the latter case, the
socalled “body eﬀect” must be accounted for when analyzing the circuit. Figure 1: MOSFET symbols. Device Equations
The discussion here applies to the nchannel MOSFET. The equations apply to the pchannel device if the
subscripts for the voltage between any two of the device terminals are reversed, e.g. vGS becomes vSG .
The nchannel MOSFET is biased in the active mode or saturation region for vDS ≥ vGS − vT H , where
vT H is the threshold voltage. This voltage is negative for the depletionmode device and positive for the
enhancementmode device. It is a function of the bodysource voltage and is given by
vT H = VT O + γ φ − vBS − φ (1) where VT O is the value of vT H with vBS = 0, γ is the body threshold parameter, φ is the surface potential,
and vBS is the bodysource voltage. The drain current is given by
iD = kW
(1 + λvDS ) (vGS − vT H )2
2L (2) where W is the channel width, L is the channel length, λ is the channellength modulation parameter, and
k is given by
ox
k = µ0 Cox = µ
(3)
tox 1 In this equation, µ0 is the average carrier mobility, Cox is the gate oxide capacitance per unity area, ox is
the permittivity of the oxide layer, and tox is its thickness. It is convenient to deﬁne a transconductance
coeﬃcient K given by
kW
K=
(1 + λvDS ) = K0 (1 + λvDS )
(4)
2L
where K0 is given by
kW
(5)
K0 =
2L
With these deﬁnitions, the drain current can be written
iD = K (vGS − vT H )2 (6) Note that K plays the same role in the MOSFET drain current equation as β plays in the JFET drain
current equation.
Some texts deﬁne K = k (W/L) (1 + λvDS ) so that iD is written iD = (K/2) (vGS − vT H )2 . In this case,
the numerical value of K is twice the value used here. To modify the equations given here to conform to
this usage, replace K in any equation given here with K/2. Transfer and Output Characteristics
The transfer characteristics are a plot of the drain current iD as a function of the gatetosource voltage
vGS with the draintosource voltage vDS held constant. Fig. 2 shows the typical transfer characteristics
for a zero bodytosource voltage. In this case, the threshold voltage is a constant, i.e. vT H = VT O . For
vGS ≤ VT O , the drain current is zero. For vGS > VT O , Eq. (6) shows that the drain current increases as the
square of the gatetosource voltage. The slope of the curve represents the smallsignal transconductance
gm , which is deﬁned in the following. Figure 2: Drain current iD versus gatetosource voltage vGS for constant draintosource voltage vDS .
The output characteristics are a plot the drain current iD as a function of the draintosource voltage
vDS with the gatetosource voltage vGS and the bodytosource voltage vBS held constant. Fig. 3 shows the
typical output characteristics for several values of gatetosource voltage vGS . The dashed line divides the
triode region from the saturation or active region. In the saturation region, the slope of the curves represents
the reciprocal of the smallsignal drainsource resistance r0 , which is deﬁned in the next section. SmallSignal Models
There are two smallsignal circuit models which are commonly used to analyze MOSFET circuits. These are
the hybridπ model and the T model. The two models are equivalent and give identical results. They are
described below. In addition, a simpliﬁed smallmodel is derived which is called the source equivalent circuit.
The models are ﬁrst developed for the case of no body eﬀect and then with the body eﬀect. The former
2 Figure 3: Drain current iD versus draintosource voltage vDS for constant gatetosource voltage vGS .
case assumes that the bodysource voltage is zero, i.e. vBS = 0. This is the case with discrete MOSFETs
in which the source is connected physically to the body. It also applies to smallsignal ac analyses for which
the body and source leads are connected to the same or diﬀerent dc voltages. In this case, the smallsignal
bodysource voltage is zero, i.e. vbs = 0, and there is no body eﬀect. No Body Eﬀect
The smallsignal models in this section assume that the body lead is connected to the source lead. The
models also apply when the body and source leads are connected to diﬀerent dc voltages so that the ac or
signal voltage from body to source is zero. Hybridπ Model
Consider the case where the bodysource voltage is zero, i.e. vBS = 0. In this case, the threshold voltage in
Eq. 1 is a constant and given by vT H = VT O . Let the drain current and each voltage be written as the sum
of a dc component and a smallsignal ac component as follows:
iD = I D + id (7) vGS = VGS + vgs (8) vDS = VDS + vds (9) If the ac components are suﬃciently small, we can write
id = ∂ID
∂ID
vgs +
vds
∂VGS
∂VDS (10) where the derivatives are evaluated at the dc bias values. Let us deﬁne
gm =
r0 = ∂ ID
∂VDS ∂ID
= K (VGS − VT H ) = 2 K ID
∂VGS −1 = kW
λ (VGS − VT H )2
2L −1 = 1/λ + VDS
ID (11) (12) It follows that the smallsignal drain current can be written
id = id +
3 vds
r0 (13) where
id = gm vgs (14) The smallsignal circuit which models these equations is given in Fig. 4(a). This is called the hybridπ
model. Figure 4: (a) Hybridπ model. (b) T model. T Model
The T model of the MOSFET is shown in Fig. 4(b). The resistor r0 is given by Eq. (12). The resistor rs is
given by
1
rs =
(15)
gm
where gm is the transconductance deﬁned in Eq. (11). The currents are given by
id = is +
is = vds
r0 (16) vgs
= gm vgs
rs (17) The currents in the T model are the same as for the hybridπ model. Therefore, the two models are equivalent.
Note that the gate and body currents in Fig. 4(b) are zero because the controlled source supplies the current
that ﬂows through rs . The Drain Equivalent Circuit
If the FET output is taken from the drain, the input can be either applied to the gate or to the source. If
it is applied to the gate, the circuit is called a commonsource ampliﬁer. If it is applied to the source, the
circuit is called a commongate ampliﬁer. In some cases, separate inputs can be applied to both the gate and
the source. In any of these cases, the drain output can be solved for by ﬁrst making a smallsignal Thévenin
or Norton equivalent circuit seen looking into the drain. We solve for the Norton equivalent circuit here. We
assume that the circuits external to the gate and the source can be represented by Thévenin equivalents.
Figure 5(a) shows the FET symbol with separate Thévenin sources connected to the gate and the source.
The bias circuits are not shown, but we assume that the bias solutions are known. Figure 5(b) shows the
circuit with the FET replaced with the hybridπ model.
The Norton equivalent circuit seen looking into the drain consists of a parallel current source id(sc) and
resistor rid connecting between the drain and ground. This is shown in Figure 5(c). The value of id(sc) is
the drain current with vd = 0, i.e. with the drain node grounded. From Figure 5(b), this current is given by
id(sc) = id + i0 4 id (18) Figure 5: (a) FET with Thevenin sources connected to the gate and the source. (b) Circuit with the FET
replaced with its hybridπ model. (c) Drain Norton equivalent circuit.
where the approximation assumes that the current i0 through r0 is small compared to id . This is usually a
very good approximation because r0 is a large value resistor. We call it the “r0 approximation” when the
current i0 is neglected. In many cases, r0 is taken to be an inﬁnite resistor, in which case the approximation
is exact.
To solve for id , we can write the loop equation
vtg − vts = vgs + is Rts
= vgs + (is + i0 ) Rts
id
=
+ (id + i0 ) Rts
gm
1
id
+ Rts
gm (19) where the relations vgs = id /gm and is = id have been used. It follows that we can write
id(sc) = id = Gm (vtg − vts ) (20) where Gm is an equivalent transconductance given by
Gm = 1
1
or
=
1
rs + Rts
+ Rts
gm (21) where rs = 1/gm .
We next solve for the resistance rid seen looking into the drain node. Consider the drain current id to be
an independent current source and set vtg = vts = 0. We can write
vd = i0 r0 + is Rts
= (id − id ) r0 + is Rts
= id (r0 + Rts ) − id r0 id = gm vgs = −gm vs = −gm is Rts = −gm id Rts (22)
(23) where vgs = −vs and is = id have been used. Substitution of id from the second equation into the ﬁrst
equation yields
vd = id (r0 + Rts ) + gm id Rts r0
= id [r0 (1 + gm Rts ) + Rts ]
5 (24) It follows that the drain resistance is given by
rid = vd
Rts
or
= r0 (1 + gm Rts ) + Rts = r0 1 +
id
rs + Rts (25) Note that no approximations have been made in solving for rid .
In summary, the smallsignal Norton equivalent circuit seen looking into the drain of a FET is a current
source id(sc) in parallel with a resistor rid given by
id(sc) = id = Gm (vtg − vts )
Gm = (26) 1
1
or
=
1
rs + Rts
+ Rts
gm
or rid = r0 (1 + gm Rts ) + Rts = r0 1 + Rts
rs (27) + Rts (28) where vtg and vts , respectively, are the Thévenin voltages seen looking out of the gate and source and Rts
is the Thévenin resistance in series with vts . Note that Rtg does not appear in the equations because the
current through it is zero.
Example 1 Figure 6(a) shows the signal equivalent circuit of a commonsource ampliﬁer. It is given that
Rtg = 1 k , Rts = 50 , RD = 10 k , ID = 1 mA, K = 1.5 mA/ V2 , and r0 = 50 k . Solve for the voltage
gain and output resistance of the circuit. Figure 6: (a) Commonsource ampliﬁer. (b) Commongate ampliﬁer. (c) Commondrain ampliﬁer.
√
Solution: gm = 2 KID = 2.45 mS, rs = 1/gm = 408 .
A ﬂow graph for the voltage gain is shown in Figure 7(a). From the ﬂow graph, we can write
vo
i
vo
= d×
= Gm × − (rid RD )
vtg
vtg
id
The numerical values are
Gm = 1
1
=
rs + Rts
458 6 (29) (30) rid Rts
+ Rts
rs
50
= 50k 1 +
+ 50 = 56.2 k
408
= r0 1 + 1
vo
56.2k × 10k
= Gm × − (rid RC ) =
×−
= −18.5
vtg
458
56.2k + 10k
56.2k × 10k
= 8.49 k
56.2k + 10k
Because the gain is negative, the ampliﬁer is said to be an inverting ampliﬁer.
rout = rid RD = (31)
(32)
(33) Figure 7: (a) Flow graph for the CS ampliﬁer. (b) Flow graph for the CG ampliﬁer.
Example 2 Figure 6(b) shows the signal equivalent circuit of a commongate ampliﬁer. It is given that
Rts = 50 , RD = 10 k , ID = 1 mA, K = 1.5 mA/ V2 , and r0 = 50 k . Solve for the voltage gain and
output resistance of the circuit.
√
Solution: gm = 2 KID = 2.45 mS, rs = 1/gm = 408 .
A ﬂow graph for the voltage gain is shown in Figure 7(b). From the ﬂow graph, we can write
vo
i
vo
= d×
= −Gm × − (rid RC )
vts
vts
id
The numerical values are
Gm = rid 1
1
1
=
=
rs + Rts
408 + 50
458 Rts
+ Rts
rs
50
= 50k 1 +
+ 50 = 56.2 k
408
= r0 1 + vo
1
56.2k × 10k
= −Gm × − (rid RC ) =
×
= 18.5
vtg
458 56.2k + 10k
56.2k × 10k
= 8.49 k
56.2k + 10k
Because the gain is positive, the ampliﬁer is said to be a noninverting ampliﬁer.
rout = rid RD = The Gate Equivalent Circuit
Because the gate current ig = 0, the equivalent circuit seen looking into the gate is an open circuit. 7 Figure 8: (a) BJT symbol with a Thévenin source connected to the base. (b) Circuit with the BJT replaced
with its hybridπ model. (c) Thévenin emitter equivalent circuit. The Source Equivalent Circuit
Figure 8(a) shows the FET symbol with a Thévenin source connected to the gate. The bias circuits are not
shown, but we assume that the bias solutions are known. We wish to solve for the smallsignal Thévenin
equivalent circuit seen looking into the source. Figure 8(b) shows the circuit with the FET replaced with
the hybridπ model.
From the circuit in 8(b), we can write
vs = vtg − vgs
i
= vtg − d
gm
i
= vtg − s
gm
is − i0
= vtg −
gm
is
vtg −
gm (34) where the approximation assumes i0 is small compared to is has been used. It follows that the Thévenin
equivalent circuit seen looking into the source is the voltage source vtg in series with a resistance ris given
by
1
ris =
= rs
(35)
gm
The equivalent circuit is shown in Figure 8(c). There is no Rtg in this solution because the current through
it is zero.
With the deﬁnition of ris , we can deﬁne another way of calculating id(sc) in the Norton drain circuit.
The current is in Figure 5(a) is given by
vtg − vts
is =
(36)
ris + Rts
Because id = is is and id(sc) = id = Gm (vtg − vts ), we have a third equation for Gm given by
Gm = 1
ris + Rts (37) Example 3 Figure 6(c) shows the signal equivalent circuit of a commondrain ampliﬁer. It is given that
Rtg = 10 k , Rts = 1 k , ID = 1 mA, K = 1.5 mA/ V2 , and r0 = 50 k . Solve for the voltage gain and
output resistance of the circuit.
8 √
Solution: gm = 2 KID = 2.45 mS, rs = 1/gm = 408 .
ris = rs =
Gm = 1
= 408
gm 1
1
1
=
=
ris + Rts
408 + 1k
1408 The output resistance is
rout = ris Rts = 408 × 1k
= 290
408 + 1k The input resistance is an open circuit.
Two possible ﬂow graphs for the solution are shown in Figure 9. Figure 9: Flow graphs for the commoncollector ampliﬁer.
The ﬁrst solution for the voltage gain is illustrated in Figure 9(a), where voltage division is used to solve
for the gain to obtain
vo
Rts
1k
=
=
= 0.710
vtg
ris + Rts
408 + 1k
The second solution is illustrated in Figure 9(b). The voltage gain is
vo
i
is
vo
1
= d× ×
= Gm × 1 × Rts =
× 1 × 1k = 0.710
vtg
vtg
id
is
1408
Example 4 Figure 10(a) shows a CS/CD ampliﬁer. What are the expressions for the input resistance, the
output resistance, and the voltage gain?
Solution: Because ig1 = 0, the input resistance is an open circuit, i.e. rin = ∞. The output resistance is
rout = ris2 RS 2
where ris2 = rs2 = 1/gm2 . A ﬂow graph for the voltage gain is shown in Figure 11(a). The gain is given by
vo
i
vtg2
vo
RS 2
= d1 ×
×
= Gm1 × − (rid1 RD1 ) ×
vtg
vtg
id1
vtg2
ris2 + RS 2
where Gm1 = 1/ (ris1 + RS 1 ) and rid1 = r01 (1 + gm1 RS 1 ) + RS 1 .
Example 5 Figure 10(b) shows a combination CS ampliﬁer and a CD/CG ampliﬁer. What are the expressions for the input resistances, the output resistance, and the output voltage?
Solution: Because ig1 == ig2 = 0, both input resistances are open circuits, i.e. rin1 = rin2 = ∞. The output
resistance is
rout = rid1 RD1
where ris1 = RS + ris2 = RS + 1/gm2 . A ﬂow graph for the output voltage is shown in Figure 12. It is given
by
vo = id1 × rid1 RD1 = Gm1 × (vtg1 − vts1 ) × rid1 RD1 = Gm1 × (vtg1 − vtg2 ) × rid1 RD1 9 Figure 10: (a) CS/CD ampliﬁer. (b) Combination CS ampliﬁer and CD/CG ampliﬁer. Figure 11: Flow graph for the CS/CD ampliﬁer. 10 where
Gm1 = 1
=
ris1 + RS + ris2 1
1
gm1 rid1 = r01 1 + gm1 RS + 1
gm2 + RS + 1
gm2 + RS + 1
gm2 Figure 12: Flow graph for the combination CS ampliﬁer and CD/CG ampliﬁer. The Body Eﬀect
The smallsignal models above assume that the body lead is connected to the source lead. In the following,
we assume that the body lead is connected to ac signal ground. In integrated circuit design, this ac signal
ground is typically a dc power supply rail. In this case, any ac signal voltage on the source lead causes an
ac signal voltage between the body and source. The eﬀect of this voltage is called the body eﬀect.
Hybridπ Model
Let the drain current and each voltage be written as the sum of a dc component and a smallsignal ac
component as follows:
iD = I D + id
(38)
vGS = VGS + vgs (39) vBS = VBS + vbs (40) vDS = VDS + vds (41) If the ac components are suﬃciently small, we can write
id = ∂ID
∂ID
∂ID
vgs +
vbs +
vds
∂VGS
∂VBS
∂VDS (42) where the derivatives are evaluated at the dc bias values. Let us deﬁne
∂ID
= K (VGS − VT H ) = 2 K ID
∂VGS
√
∂ID
γ KID
gmb =
=√
= χgm
∂VBS
φ − VBS
γ
χ= √
2 φ − VBS gm = r0 = ∂ ID
∂VDS −1 = kW
λ (VGS − VT H )2
2L 11 −1 = VDS + 1/λ
ID (43)
(44)
(45)
(46) The smallsignal drain current can thus be written
id = id + vds
r0 id = idg + idb (47) where
idg = gm vgs (48) idb = gmb vbs (49) The smallsignal circuit which models these equations is given in Fig. 13(a). This is called the hybridπ
model. If the body (B) lead is connected to the source, then vbs = 0 and the circuit becomes that given in
Fig. 4(a). Figure 13: (a) Hybridπ model with body eﬀect. (b) T model with body eﬀect. T Model
The T model of the MOSFET is shown in Fig. 4(b). The resistor r0 is given by Eq. (12). The resistors rs
and rsb are given by
1
rs =
(50)
gm
rsb = 1
1
rs
=
=
gmb
χgm
χ (51) where gm and gmb are the transconductances deﬁned in Eqs. (43) and (44). The currents are given by
id = isg + isb + vds
r0 vgs
= gm vgs
rs
vbs
=
= gmb vbs
rsb (52) isg = (53) isb (54) The currents are the same as for the hybridπ model. Therefore, the two models are equivalent. Note that
the gate and body currents are zero because the two controlled sources supply the currents that ﬂow through
rs and rsb . 12 A Simpliﬁed T Model
There is a simpliﬁcation to the T model with body eﬀect that simpliﬁes many calculations. Figure 14(a)
shows the T model of the MOSFET with a Thévenin source connected to the gate and the body connected
to signal ground. We desire the Thévenin equivalent circuit seen looking up into the is branch. The open
circuit or Thévenin voltage is given by voc 1
vtg
vtg
rsb
gmb
= vtg
= vtg
=
gmb = 1 + χ
1
1
rsg + rsb
1+
+
gm
gm gmb (55) The Thévenin resistance is calculated with vtg = 0. Let this be denoted by rs . It is given by
rs = rs rsb = rs rsb
rs or
1
=
=
rs + rsb
1+χ
(1 + χ) gm (56) Figure 14(b) shows the simpliﬁed T model. For the case where the body and the source connect to the same
signal node, set χ = 0 in the equations. Figure 14: (a) T model with a Thévenin source connected to the gate and the body grounded. (b) Simpliﬁed
T mode. The Drain Equivalent Circuit
Figure 15(a) shows the MOSFET with Thévenin sources connected to the gate and source leads. We wish to
solve for the Norton equivalent circuit seen looking into the drain. The circuit consists of a parallel current
source id(sc) and resistor rid connecting between the drain and ground. The value of id(sc) is the drain current
with vd = 0, i.e. with the drain node grounded. From the simpliﬁed T model circuit in Figure 15(b), this
current is given by
id(sc) = id + i0 id
(57)
where the approximation assumes that the current i0 through r0 is small compared to id . This is usually a
very good approximation because r0 is a large value resistor. We call it the “r0 approximation” when the
current i0 is neglected. In many cases, r0 is taken to be an inﬁnite resistor, in which case the approximation
is exact.
To solve for id , we can write the loop equation
vtg
− vts = is rs + is Rts = is rs + (is + i0 ) Rts = id rs + (id + i0 ) Rts
1+χ
13 id (rs + Rts ) (58) Figure 15: (a) MOSFET with Thévenin sources connected to the gate and the source. (b) Simpliﬁed T
model of the circuit. (c) Norton equivalent drain circuit.
From this equation, it follows that we can write
id(sc) = id = Gm (vtg − vts ) (59) where Gm is an equivalent transconductance given by
Gm = 1
or
=
rs + Rts 1
1
or
=
rs
1
+ Rts
+ Rts
1+χ
(1 + χ) gm (60) We next solve for the resistance rid seen looking into the drain node. Consider the drain current id to be
an independent current source and set vtg = vts = 0. We can write
vd = i0 r0 + is Rts = (id − id ) r0 + is Rts = id (r0 + Rts ) − id r0
id = is = (61) vgs
is Rts
id Rts
=−
=−
rs
rs
rs where vgs = −vs = −is Rts and is = id have been used. Substitution of id from the second equation into the
ﬁrst equation yields
vd = id (r0 + Rts ) − id r0 = id (r0 + Rts ) + id Rts
Rts
r0 = id r0 1 +
rs
rs + Rts (62) It follows that the drain resistance is given by
rid = Rts
vd
= r0 1 +
id
rs or + Rts = r0 1 + (1 + χ) Rts
or
+ Rts = r0 [1 + (1 + χ) gm Rts ] + Rts
rs (63) Note that no approximations have been made in solving for rid .
In summary, the smallsignal Norton equivalent circuit seen looking into the drain of a FET is a current
source id(sc) in parallel with a resistor rid given by
id(sc) = id = Gm 14 vtg
− vts
1+χ (64) Gm = rid = r0 1 + Rts
rs 1
or
=
rs + Rts 1
1
or
=
rs
1
+ Rts
+ Rts
1+χ
(1 + χ) gm or + Rts = r0 1 + (1 + χ) Rts
or
+ Rts = r0 [1 + (1 + χ) gm Rts ] + Rts
rs (65) (66) where vtg and vts , respectively, are the Thévenin voltages seen looking out of the gate and source and Rts
is the Thévenin resistance in series with vts . Note that Rtg does not appear in the equations because the
current through it is zero.
The Source Equivalent Circuit
The source equivalent circuit is derived above for the case where the body lead is connected to the MOSFET
gate. The circuit derived here is for the case where the body is connected to signal ground. Figure 16(a)
shows the MOSFET symbol with a Thévenin equivalent source connected to the gate. The equation for the
source voltage vs follows from the simpliﬁed T model circuit in Figure 14(b). It is given by
vs = vtg
vtg
− is rs =
− (is − i0 ) rs
1+χ
1+χ vtg
− is rs
1+χ (67) where the approximation assumes that i0 is small compared to is . It follows that the source equivalent
circuit consists of a voltage source vs(oc) in series with a resistance ris given by
vs(oc) = vtg
1+χ ris = rs = 1
rs
=
1+χ
(1 + χ) gm (68) The circuit is shown in Figure 16(b). Figure 16: (a) MOSFET with Thevenin source connected to the gate and the body connected to signal
ground. (b) Source equivalent circuit. Summary of Models
id(sc) = id = Gm
or Gm = 1
or
=
rs + Rts
rs = 1
gm vtg
− vts
1+χ 1
1
1
or
or
=
=
rs
1
ris + Rts
+ Rts
+ Rts
1+χ
gm (1 + χ)
ris = rs = 15 rs or
1
=
1+χ
gm (1 + χ) (69)
(70) (71) Figure 17: Summary of the equivalent circuits. rid = r0 1 + Rts
rs Rts
or
+ Rts = r0 [1 + (1 + χ) gm Rts ] + Rts
rs or + Rts = r0 1 + (1 + χ) rig = ∞ (72)
(73) Set χ = 0 when the body is connected to the source or when the body and the source are connected to the
same node. SmallSignal HighFrequency Models
Figures 18 and 19 show the hybridπ and T models for the MOSFET with the gatesource capacitance
cgs , the sourcebody capacitance csb , the drainbody capacitance cdb , the draingate capacitance cdg , and
the gatebody capacitance cgb added. These capacitors model charge storage in the device which aﬀect its
highfrequency performance. The ﬁrst three capacitors are given by
2
cgs = W LCox
3
csb =
cdb = csb0
(1 + VSB /ψ0 )1/2
cdb0
(1 + VDB /ψ0 )1/2 (74)
(75)
(76) where VSB and VDB are dc bias voltages; csb0 and cdb0 are zerobias values; and ψ0 is the builtin potential.
Capacitors cgd and cgb model parasitic capacitances. For IC devices, cgd is typically in the range of 1 to 10
fF for small devices and cgb is in the range of 0.04 to 0.15 fF per square micron of interconnect. 16 Figure 18: Highfrequency hybridπ model. Figure 19: Highfrequency T model. 17 ...
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This note was uploaded on 05/26/2011 for the course ECE 3050 taught by Professor Hollis during the Summer '08 term at Georgia Institute of Technology.
 Summer '08
 HOLLIS
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