eee410_lecture5 - EEE 410 Microprocessors I Fall 04/05...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
EEE 410 – Microprocessors I Fall 04/05 – Lecture Notes # 5 Outline of the Lecture Flag Registers and bit fields 80x86 addressing modes. F LAG R EGISTERS AND BIT FIELDS Flag Register and ADD instruction The flag bits affected by the ADD instructions are: CF, PF, AF, ZF, SF and OF. The OF will be studied in Chapter 6. Ex: Show how the flag register is affected by the addition of 38H and 2FH. Solution: MOV BH,38H ;BH=38H ADD BH,2FH ;BH = BH + 2F = 38 + 2F= 67H 38 0011 1000 + 2F 0010 1111 67 0110 0111 CF = 0 since there is no carry beyond d7 PF = 0 since there is odd number of 1`s in the result AF = 1 since there is a carry from d3 to d4 ZF = 0 since the result is not zero SF = 0 since d7 of the result is zero Ex: Show how the flag register is affected by the following addition Solution: MOV AX,34F5H ;AX =34F5H ADD AX,95EBH ;AX = CAE0H 34F5 0011 0100 1111 0101 + 95EB 1001 0101 1110 1011 CAE0 1100 1010 1110 0000 CF = 0 since there is no carry beyond d15 PF = 0 since there is odd number of 1s in the lower byte AF = 1 since there is a carry from d3 to d4 ZF = 0 since the result is not zero SF = 1 since d15 of the result is 1 ¾ Note that the MOV instructions have no effect on the flag (Explain on the existing example) Use of zero flag for looping
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 4

eee410_lecture5 - EEE 410 Microprocessors I Fall 04/05...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online