eee410_lecture20 - EEE 410 Microprocessors I Spring 04/05...

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1 EEE 410 – Microprocessors I Spring 04/05 – Lecture Notes # 20 Outline of the Lecture Interfacing the Serial Port Serial Port registers Transmitting Serial Data Receiving Serial Data I NTERFACING THE S ERIAL P ORT Serial Port’s Registers (PC’s) ¾ Name Address IRQ COM 1 3F8 4 COM 2 2F8 3 COM 3 3E8 4 COM 4 2E8 3 Table : Standard Port Addresses ¾ Above is the standard port addresses. These should work for most P.C's. However some PCs can have different set of addresses and IRQ's. Just like the LPT ports, the base addresses for the COM ports can be read from the BIOS Data Area. Start Address Function 0000:0400 COM1's Base Address 0000:0402 COM2's Base Address 0000:0404 COM3's Base Address 0000:0406 COM4's Base Address Table - COM Port Addresses in the BIOS Data Area; ¾ The above table shows the address at which we can find the Communications (COM) ports addresses in the BIOS Data Area. ¾ Table of Registers of UART Base Address DLAB Read/Write Abr. Register Name =0 Write - Transmitter Holding Buffer =0 Read - Receiver Buffer + 0 =1 Read/Write - Divisor Latch Low Byte =0 Read/Write IER Interrupt Enable Register + 1 =1 Read/Write - Divisor Latch High Byte - Read IIR Interrupt Identification Register + 2 - Write FCR FIFO Control Register + 3 - Read/Write LCR Line Control Register + 4 - Read/Write MCR Modem Control Register + 5 - Read LSR Line Status Register + 6 - Read MSR Modem Status Register + 7 - Read/Write - Scratch Register Table : Table of Registers
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2 ¾ DLAB ? You will have noticed in the table of registers that there is a DLAB column. When DLAB is set to '0' or '1' some of the registers change. This is how the UART is able to have 12 registers (including the scratch register) through only 8 port addresses. DLAB stands for Divisor Latch Access Bit . When DLAB is set to '1' via the line control register , two registers become available from which you can set your speed of communications measured in bits per second. The UART will have a crystal which should oscillate around 1.8432 MHZ. The UART incorporates a divide by 16 counter which simply divides the incoming clock signal by 16. Assuming we had the 1.8432 MHZ clock signal, that would leave us with a maximum, 115,200 hertz signal making the UART capable of transmitting and receiving at 115,200 Bits Per Second (BPS) . That would be fine for some of the faster modems and devices which can handle that speed, but others just wouldn't communicate at all. Therefore the UART is fitted with a Programmable Baud Rate Generator which is controlled by two registers. Ex: Lets say for example we only wanted to communicate at 2400 BPS?? We would have to divide 115,200 by 48 to get a workable 2400 Hertz Clock. The "Divisor", in this case 48, is stored in the two registers controlled by the
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eee410_lecture20 - EEE 410 Microprocessors I Spring 04/05...

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