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Unformatted text preview: Chapter 6: Interfacing Embedded System Design, Vahid/Givargis Last update: 10/20/99 5:15 PM 6-1 Chapter 6 Interfacing 6.1 Introduction As stated in the previous chapter, we use processors to implement processing, memories to implement storage, and buses to implement communication. The earlier chapters described processors and memories. This chapter describes implementing communication with buses, i.e., interfacing. Buses implement communication among processors or among processors and memories. Communication is the transfer of data among those components. For example, a general-purpose processor reading or writing a memory is a common form of communication. A general-purpose processor reading or writing a peripherals register is another common form. A bus consists of wires connecting two or more processors or memories. Figure 6.1(a) shows the wires of a simple bus connecting a processor with a memory. Note that each wire may be uni-directional, as are rd/wr, enable , and addr , or bi-directional, as is data . Also note that a set of wires with the same function is typically drawn as a thick line (or a line with a small angled line drawn through it). addr and data each represent a set of wires; the addr wires transmit an address, while the data wires transmit data. The bus connects to "pins" of a processor (or memory). A pin is the actual conducting device (i.e., metal) on the periphery of a processor through which a signal is input to or output from the processor. When a processor is packaged as its own IC, there are actual pins extending from the package, designed to be plugged into a socket on a printed-circuit board. Today, however, a processor commonly co-exists on a single IC with other processors and memories. Such a processor does not have any actual pins on its periphery, but rather "pads" of metal in the IC. In fact, even for a processor packaged in its own IC, alternative packaging-techniques may use something other than pins for connections, such as small metallic balls. For consistency, though, we shall use the term pin in this chapter regardless of the packaging situation. A bus must have an associated protocol describing the rules for transferring data over those wires. We deal primarily with low-level hardware protocols in this chapter, while higher-level protocols, like IP (Internet Protocol) can be built on top of these protocols, using a layered approach. Interfacing with a general-purpose processor is extremely common. We describe three issues relating to such interfacing: addressing, interrupts, and direct memory access. When multiple processors attempt to access a single bus or memory simultaneously, resource contention exists. This chapter therefore describes several schemes for arbitrating among the contending processors....
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This note was uploaded on 06/02/2011 for the course CS 550 taught by Professor Young during the Spring '11 term at New York Institute of Technology-Westbury.
- Spring '11