ch6_030702 - 1 Embedded Systems Design: A Unified...

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Unformatted text preview: 1 Embedded Systems Design: A Unified Hardware/Software Introduction Chapter 6 Interfacing 2 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis Outline Interfacing basics Microprocessor interfacing I/O Addressing Interrupts Direct memory access Arbitration Hierarchical buses Protocols Serial Parallel Wireless 3 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis Embedded system functionality aspects Processing Transformation of data Implemented using processors Storage Retention of data Implemented using memory Communication Transfer of data between processors and memories Implemented using buses Called interfacing Introduction 4 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis A simple bus bus structure Processor Memory rd'/wr enable addr[0-11] data[0-7] bus Wires: Uni-directional or bi-directional One line may represent multiple wires Bus Set of wires with a single function Address bus, data bus Or, entire collection of wires Address, data and control Associated protocol: rules for communication 5 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis Ports Conducting device on periphery Connects bus to processor or memory Often referred to as a pin Actual pins on periphery of IC package that plug into socket on printed-circuit board Sometimes metallic balls instead of pins Today, metal pads connecting processors and memories within single IC Single wire or set of wires with single function E.g., 12-wire address port bus Processor Memory rd'/wr enable addr[0-11] data[0-7] port 6 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis Timing Diagrams write protocol rd'/wr enable addr data t setup t write Most common method for describing a communication protocol Time proceeds to the right on x-axis Control signal: low or high May be active low (e.g., go, /go, or go_L) Use terms assert (active) and deassert Asserting go means go=0 Data signal: not valid or valid Protocol may have subprotocols Called bus cycle, e.g., read and write Each may be several clock cycles Read example rd/wr set low,address placed on addr for at least t setup time before enable asserted, enable triggers memory to place data on data wires by time t read read protocol rd'/wr enable addr data t setup t read 7 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis Basic protocol concepts Actor: master initiates, servant (slave) respond Direction: sender, receiver Addresses: special kind of data Specifies a location in memory, a peripheral, or a register within a peripheral Time multiplexing Share a single set of wires for multiple pieces of data...
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ch6_030702 - 1 Embedded Systems Design: A Unified...

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