Project Phase I

Project Phase I - EE479 Class Project Phase I Opamp Supply-Independent Bias Current Generator 1 Introduction This purpose of the final project is

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EE479 Class Project Phase I Opamp Supply-Independent Bias Current Generator 1. Introduction This purpose of the final project is to design a state-of-the-art Low-Voltage, Low-Power, High-Speed, High-Gain CMOS operational amplifier in the TSMC 180nm CMOS technology process. 2. Required Performance Table 1 summarizes the required performance for your designed final CMOS operational amplifier. It also indicates the priorities of performance parameters. Note: we want the CMOS operational amplifier to be compatible to P-Well, N-Well, or twin-Well processes, all the pMOS body (substrate) terminals must be connected to VDD and all the nMOS body (substrate) terminals must be connected to VSS (ground). Parameter Description Required Achieved Value Priority Power Supply Voltage (Vdd) 22 V -------- Temperature (Room) 25 25 °C -------- TSMC 0.18um Process Corner Typical Typical ----- -------- Output Load Capacitor 11 p F -------- Opamp Open Loop DC Gain (Avo) > 100 dB 1 Opamp Unity Gain-Bandwidth Product (UGBW) > 1 GHz 1 Phase Margin > 60 Degree 1 Settling Time (0.01% for 1V output step) < 10 ns 1 Input Voltage Range > 1 V 2 Supply Current Consumption (Idd) < 25 mA 2 Power Consumption (Vdd X Idd) < 50 mW 2 Positive Slew Rate (SR+) > 5 V/ns 3 Negative Slew Rate (SR-) > 5 V/ns 3 Common Mode Rejection Ratio (at 100Hz) > 80 dB 3 Positive Power Supply Rejection Ratio (at 100Hz) > 60 dB 3 Negative Power Supply Rejection Ratio (at 100Hz) > 60 dB 3 Table 1: CMOS Operational Amplifier Performance and Priorities.
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This note was uploaded on 06/03/2011 for the course EE 479 at USC.

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Project Phase I - EE479 Class Project Phase I Opamp Supply-Independent Bias Current Generator 1 Introduction This purpose of the final project is

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