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# para16 - Parallel Algorithms II(16 The Design of Parallel...

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The Design of Parallel Algorithms A major challenge facing computer scientists today, given the existence of massively parallel machines, is to design algorithms which exploit this parallelism. There are three main approaches to the design of parallel algorithms. 1. Modify existing sequential algorithms exploiting those parts of the algorithm that are naturally parallelizable. To some extent, this is what we did in the last set of notes with the algorithm to find the largest key from a set of keys. The tournament method (also called the binary fan-in technique) is not unique to parallel algorithms, indeed the same technique can be applied sequentially, however, that part of the algorithm is inherently parallel. 2. Design an entirely new parallel algorithm that may have no natural sequential analog. 3. For some problems, such as finding roots, the same sequential algorithm is run on many different processors concurrently with different seed values until one of the processors reports “success”. That is, all the processors start running a sequential algorithm with different initial conditions, and the first processor to achieve the desired result “wins the race.” All three of these strategies are viable is certain situations and we will see examples of each as we explore parallel algorithms further. Architectural Constraints When Designing a Parallel Algorithm A number of constraints arise when designing parallel algorithms that do not occur when designing sequential algorithms. These constraints are imposed by the architecture of the particular parallel machine on which the algorithm is intended to be executed. We eluded to some of these constraints in the last section of notes and now we will expand this discussion somewhat. There are five basic constraints that we will examine in some detail, these are: 1. Single instruction versus multiple instruction architecture. Do all the processors execute the same instruction or different instructions concurrently? 2. The number and type of processors that are available. Parallel Algorithms II - 1 Parallel Algorithms II (16)

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3. Does the architecture support the PRAM model of shared memory or does it support a distributed memory through an interconnection network? 4. Communication constraints. PRAM models have read/write restrictions while interconnection networks must specify (through a graph) the direct connections that exist between processors. 5. I/O constraints. How is the connection to the “outside world” handled. Single Instruction vs. Multiple Instruction A single-processor computer can only execute one instruction at a time. A parallel computer with p processors can execute p instructions concurrently. Each processor may operate on possibly different data. In the PRAM model, each processor executes the same instruction on possibly different data concurrently in a synchronized manner. This common instruction also contains information that can instruct a given processor to remain idle ( masked out ) during a given step.
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