{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

# AppBPOCA - B-1 Appendix B Reduction of Digital Logic...

This preview shows pages 1–9. Sign up to view the full content.

Appendix B: Reduction of Digital Logic B-1 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix B: Reduction of Digital Logic

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Appendix B: Reduction of Digital Logic B-2 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Chapter Contents B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction of Two-Level Expressions B.3 State Reduction
Appendix B: Reduction of Digital Logic B-3 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Reduction (Simplification) of Boolean Expressions • It is usually possible to simplify the canonical SOP (or POS) forms. A smaller Boolean equation generally translates to a lower gate count in the target circuit. We cover three methods: algebraic reduction, Karnaugh map re- duction, and tabular (Quine-McCluskey) reduction.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Appendix B: Reduction of Digital Logic B-4 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Reduced Majority Function Circuit • Compared with the AND-OR circuit for the unreduced majority function, the inverter for C has been eliminated, one AND gate has been eliminated, and one AND gate has only two inputs instead of three inputs. Can the function by reduced further? How do we go about it? F AC B F ABC A B C A B C A B C A B C Unreduced Reduced
Appendix B: Reduction of Digital Logic B-5 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring The Algebraic Method • Consider the majority function, F. We apply the algebraic method to reduce F to its minimal two-level form: F ABC ABC ABC F AB C C F AB F AB F AB ABC F AC B B AB F AC AB F AC AB ABC FB C =+++ =++ + + =+ + + + + + = () Distributive Property Complement Property Identity Property Idempotence Identity Property Complement and Identity Idempotence 1 ( ) A A AC AB F B CA B ++ + Distributive Complement and Identity

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Appendix B: Reduction of Digital Logic B-6 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring The Algebraic Method • This majority circuit is functionally equivalent to the previous ma- jority circuit, but this one is in its minimal two-level form: F ABC
Appendix B: Reduction of Digital Logic B-7 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Karnaugh Maps: Venn Diagram Rep- resentation of Majority Function • Each distinct region in the “Universe” represents a minterm. This diagram can be transformed into a Karnaugh Map. ABC ABC’ AB’C AB’C’ A’BC A’BC’ A’B’C A’B’C’ B A C

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Appendix B: Reduction of Digital Logic B-8 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring K-Map for Majority Function • Place a “1” in each cell that corresponds to that minterm.
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 51

AppBPOCA - B-1 Appendix B Reduction of Digital Logic...

This preview shows document pages 1 - 9. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online