Ch04POCA - 4-1 Chapter 4: The Instruction Set Architecture...

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Chapter 4: The Instruction Set Architecture 4-1 © 1999 M. Murdocca and V. Heuring Principles of Computer Architecture by M. Murdocca and V. Heuring Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 4: The Instruction Set Architecture
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Chapter 4: The Instruction Set Architecture 4-2 © 1999 M. Murdocca and V. Heuring Principles of Computer Architecture by M. Murdocca and V. Heuring Chapter Contents 4.1 Hardware Components of the Instruction Set Architecture 4.2 ARC, A RISC Computer 4.3 Pseudo-Ops 4.4 Examples of Assembly Language Programs 4.5 Accessing Data in Memory—Addressing Modes 4.6 Subroutine Linkage and Stacks 4.7 Input and Output in Assembly Language 4.8 Case Study: The Java Virtual Machine ISA
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Chapter 4: The Instruction Set Architecture 4-3 © 1999 M. Murdocca and V. Heuring Principles of Computer Architecture by M. Murdocca and V. Heuring The Instruction Set Architecture • The Instruction Set Architecture (ISA) view of a machine corre- sponds to the machine and assembly language levels. • A compiler translates a high level language, which is architecture independent, into assembly language, which is architecture de- pendent. • An assembler translates assembly language programs into ex- ecutable binary codes. • For fully compiled languages like C and Fortran, the binary codes are executed directly by the target machine. Java stops the trans- lation at the byte code level. The Java virtual machine, which is at the assembly language level, interprets the byte codes (hardware implementations of the JVM also exist, in which Java byte codes are executed directly.)
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Chapter 4: The Instruction Set Architecture 4-4 © 1999 M. Murdocca and V. Heuring Principles of Computer Architecture by M. Murdocca and V. Heuring The System Bus Model of a Computer System Bus Data Bus Address Bus Control Bus (ALU, Registers, and Control) Memory Input and Output (I/O) CPU
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Chapter 4: The Instruction Set Architecture 4-5 © 1999 M. Murdocca and V. Heuring Principles of Computer Architecture by M. Murdocca and V. Heuring Common Sizes for Data Types • A byte is composed of 8 bits. Two nibbles make up a byte. • Halfwords, words, doublewords, and quadwords are composed of bytes as shown below: Bit Nibble Byte 16-bit word (halfword) 32-bit word 64-bit word (double) 0 0110 10110000 11001001 01000110 10110100 00110101 10011001 01011000 01011000 01010101 10110000 11110011 11001110 11101110 01111000 00110101 128-bit word (quad) 01011000 01010101 10110000 11110011 11001110 11101110 01111000 00110101 00001011 10100110 11110010 11100110 10100100 01000100 10100101 01010001
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Chapter 4: The Instruction Set Architecture 4-6 © 1999 M. Murdocca and V. Heuring Principles of Computer Architecture by M. Murdocca and V. Heuring Big-Endian and Little-Endian Formats • In a byte-addressable machine, the smallest datum that can be referenced in memory is the byte. Multi-byte words are stored as a sequence of bytes, in which the address of the multi-byte word is the same as the byte of the word that has the lowest address.
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This note was uploaded on 06/13/2011 for the course CGS 3269 taught by Professor Staff during the Spring '08 term at University of Central Florida.

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Ch04POCA - 4-1 Chapter 4: The Instruction Set Architecture...

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