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Ch06POCA - 6-1 Chapter 6 Datapath and Control Principles of...

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Chapter 6: Datapath and Control 6-1 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 6: Datapath and Control
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Chapter 6: Datapath and Control 6-2 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Chapter Contents 6.1 Basics of the Microarchitecture 6.2 A Microarchitecture for the ARC 6.3 Hardwired Control 6.4 Case Study: The VHDL Hardware Description Language
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Chapter 6: Datapath and Control 6-3 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring The Fetch-Execute Cycle • The steps that the control unit carries out in executing a program are: (1) Fetch the next instruction to be executed from memory. (2) Decode the opcode. (3) Read operand(s) from main memory, if any. (4) Execute the instruction and store results. (5) Go to step 1.
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Chapter 6: Datapath and Control 6-4 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring High Level View of Microarchitecture Control Unit Control Section Registers ALU Datapath (Data Section) SYSTEM BUS The microarchitecture consists of the control unit and the pro- grammer-visible registers, functional units such as the ALU, and any additional registers that may be required by the con- trol unit.
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Chapter 6: Datapath and Control 6-5 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring ARC Instruction Subset ld Load a register from memory Mnemonic Meaning st sethi andcc addcc call jmpl be orcc orncc Store a register into memory Load the 22 most significant bits of a register Bitwise logical AND Add Branch on overflow Call subroutine Jump and link (return from subroutine call) Branch if equal Bitwise logical OR Bitwise logical NOR bneg bcs Branch if negative Branch on carry srl Shift right (logical) bvs ba Branch always Memory Logic Arithmetic Control
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Chapter 6: Datapath and Control 6-6 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring ARC Instruction Formats op3 (op=10) 010000 010001 010010 010110 100110 111000 addcc andcc orcc orncc srl jmpl 0001 0101 0110 0111 1000 cond be bcs bneg bvs ba branch 010 100 op2 branch sethi Inst. 00 01 10 11 op SETHI/Branch CALL Arithmetic Memory Format 000000 000100 ld st op3 (op=11) op CALL format disp30 3130292827262524232221201918171615141312111009080706050403020100 0 1 SETHI Format imm22 3130292827262524232221201918171615141312111009080706050403020100 rd disp22 0 cond 0 0 0 0 Branch Format op2 op2 3130292827262524232221201918171615141312111009080706050403020100 rs1 1 op3 simm13 1 op3 1 Memory Formats 1 rd rd rs1 0 1 0 0 0 0 0 0 0 0 rs2 Arithmetic Formats 3130292827262524232221201918171615141312111009080706050403020100 rs1 1 op3 simm13 1 op3 0 0 rd rd rs1 0 1 0 0 0 0 0 0 0 0 rs2 i PSR 3130292827262524232221201918171615141312111009080706050403020100 z v c n
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Chapter 6: Datapath and Control 6-7 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring ARC Datapath %r0 A bus B bus C bus F 1 F 2 ALU 32 32 4 %r1 64-to-32 MUX C Bus MUX n , z , v , c F 0 C Decoder %r5 %pc %temp0 %r2 %r3 %r4 %r6 %r7 %r8 %r9 %r10 %r30 %r31 B Decoder F 3 6 c 1 c 37 37 38 b 0 b 37 6 A Decoder 38 a 0 a 37 6 Data From Main Memory MUX Control Line (From Control Unit) %temp1 %temp2 %temp3 %ir Data To Main Memory Address To
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