Ch07POCA - 7-1 Chapter 7: Memory Principles of Computer...

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Chapter 7: Memory 7-1 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 7: Memory
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Chapter 7: Memory 7-2 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Chapter Contents 7.1 The Memory Hierarchy 7.2 Random Access Memory 7.3 Chip Organization 7.4 Commercial Memory Modules 7.5 Read-Only Memory 7.6 Cache Memory 7.7 Virtual Memory 7.8 Advanced Topics 7.9 Case Study: Rambus Memory 7.10 Case Study: The Intel Pentium Memory System
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Chapter 7: Memory 7-3 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring The Memory Hierarchy Registers Cache Main memory Secondary storage (disks) Off-line storage (tape) Fast and expensive Slow and inexpensive Increasing performance and increasing cost
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7-4 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Q D CLK Read Select Data In/Out
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7-5 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring A 0 -A m-1 D -D w-1 WR CS Memory Chip
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Chapter 7: Memory 7-6 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring A Four-Word Memory with Four Bits per Word in a 2D Organization D 3 D 2 D 1 D 0 Q 3 Q 2 Q 1 Q 0 WR CS Word 0 00 01 10 11 A 0 A 1 WR WR CS Word 1 WR CS Word 2 WR CS Word 3 2-to-4 decoder Chip Select (CS)
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7-7 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Q 3 Q 2 Q 1 Q 0 A 0 A 1 WR CS D 3 D 2 D 1 D 0 4 × 4 RAM
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Chapter 7: Memory 7-8 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 2-1/2D Organization of a 64-Word by One-Bit RAM Row Dec- oder Column Decoder (MUX/DEMUX) A 0 A 1 A 2 A 3 A 4 A 5 Data One Stored Bit Q D CLK Read Row Select Column Select Data In/Out Read/Write Control Two bits wide: One bit for data and one bit for select.
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Chapter 7: Memory 7-9 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Two Four-Word by Four-Bit RAMs are Used in Creating a Four-Word by Eight-Bit RAM A 0 A 1 WR CS D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 4 × 4 RAM Q 7 Q 6 Q 5 Q 4 Q 3 Q 2 Q 1 Q 0 4 × 4 RAM
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Chapter 7: Memory 7-10 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Two Four-Word by Four-Bit RAMs Make up an Eight-Word by Four-Bit RAM A 0 A 1 WR D 3 D 2 D 1 D 0 4 × 4 RAM Q 3 Q 2 Q 1 Q 0 4 × 4 RAM 1-to-2 decoder 0 1 A 2 CS CS CS
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Chapter 7: Memory 7-11 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Single-In-Line Memory Module 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Vcc CAS DQ1 A0 A1 DQ2 A2 A3 Vss DQ3 A4 A5 DQ4 A6 A7 DQ5 A8 A9 NC DQ6 W Vss DQ7 NC DQ8 NC RAS NC NC Vcc PIN NOMENCLATURE Address Inputs Column-Address Strobe Data In/Data Out No Connection Row-Address Strobe 5-V Supply Ground Write Enable DQ1-DQ8 CAS A0-A9 NC RAS V cc V ss W • Adapted
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Ch07POCA - 7-1 Chapter 7: Memory Principles of Computer...

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