Ch08POCA - 8-1 Chapter 8: Input and Output Principles of...

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Chapter 8: Input and Output 8-1 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 8: Input and Output
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Chapter 8: Input and Output 8-2 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Chapter Contents 8.1 Simple Bus Architectures 8.2 Bridge-Based Bus Architectures 8.3 Communication Methodologies 8.4 Case Study: Communication on the Intel Pentium Architecture 8.5 Mass Storage 8.6 Input Devices 8.7 Output Devices
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Chapter 8: Input and Output 8-3 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Simple Bus Architecture • A simplified motherboard of a personal computer (top view): Motherboard I/O Bus Board traces (wires) Connectors for plug-in cards Integrated Circuits Plug-in card I/O bus connector Memory CPU
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Chapter 8: Input and Output 8-4 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring CPU Disk Memory Control ( C 0 C 9 ) Address ( A 0 A 31 ) Data ( D 0 D 31 ) Power (GND, +5V, –15V)
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Chapter 8: Input and Output 8-5 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring 100 MHz Bus Clock Crystal Oscillator 10101010 Logical 0 (0V) Logical 1 (+5V) 10 ns
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Chapter 8: Input and Output 8-6 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring The Synchronous Bus • Timing diagram for a synchronous memory read (adapted from [Tanenbaum, 1999]). Φ Address Data MREQ RD T 1 T 2 T 3 Leading edge Trailing edge Data valid Time Address valid
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Chapter 8: Input and Output 8-7 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring The Asynchronous Bus • Timing diagram for asynchronous memory read (adapted from [Tanenbaum, 1999]). Address MSYN RD Data Time Memory address to be read MREQ SSYN Data valid
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Chapter 8: Input and Output 8-8 Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Bus Arbitration • (a)Simple centralized bus arbitration; (b) centralized arbitration with priority levels; (c) decentralized bus arbitration. (Adapted from [Tanenbaum, 1999]). Arbiter Bus grant Bus request 0 1 2 n . . . (a) Arbiter Bus grant level 0 Bus request level 0 0 1 2 n . . . (b) Bus grant Bus request 0 1 2 n . . . (c) Busy +5V Bus grant level k Bus request level k .
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Ch08POCA - 8-1 Chapter 8: Input and Output Principles of...

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