Ch09_ECOA2e - Chapter 9 Alternative Architectures Chapter 9...

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Chapter 9 Alternative Architectures
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2 Chapter 9 Objectives Learn the properties that often distinguish RISC from CISC architectures. Understand how multiprocessor architectures are classified. Appreciate the factors that create complexity in multiprocessor systems. Become familiar with the ways in which some architectures transcend the traditional von Neumann paradigm.
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3 9.1 Introduction We have so far studied only the simplest models of computer systems; classical single-processor von Neumann systems. This chapter presents a number of different approaches to computer organization and architecture. Some of these approaches are in place in today’s commercial systems. Others may form the basis for the computers of tomorrow.
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4 9.2 RISC Machines The underlying philosophy of RISC machines is that a system is better able to manage program execution when the program consists of only a few different instructions that are the same length and require the same number of clock cycles to decode and execute. RISC systems access memory only with explicit load and store instructions. In CISC systems, many different kinds of instructions access memory, making instruction length variable and fetch-decode-execute time unpredictable.
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5 9.2 RISC Machines The difference between CISC and RISC becomes evident through the basic computer performance equation: RISC systems shorten execution time by reducing the clock cycles per instruction. CISC systems improve performance by reducing the number of instructions per program.
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6 9.2 RISC Machines The simple instruction set of RISC machines enables control units to be hardwired for maximum speed. The more complex-- and variable-- instruction set of CISC machines requires microcode-based control units that interpret instructions as they are fetched from memory. This translation takes time. With fixed-length instructions, RISC lends itself to pipelining and speculative execution.
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7 mov ax, 0 mov bx, 10 mov cx, 5 Begin add ax, bx loop Begin 9.2 RISC Machines Consider the the program fragments: The total clock cycles for the CISC version might be: (2 movs × 1 cycle) + (1 mul × 30 cycles) = 32 cycles While the clock cycles for the RISC version is: (3 movs × 1 cycle) + (5 adds × 1 cycle) + (5 loops × 1 cycle) = 13 cycles With RISC clock cycle being shorter, RISC gives us much faster execution speeds. mov ax, 10 mov bx, 5 mul bx, ax CISC RISC
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9.2 RISC Machines Because of their load-store ISAs, RISC architectures require a large number of CPU registers. These register provide fast access to data during sequential program execution. They can also be employed to reduce the overhead typically caused by passing parameters to subprograms. Instead of pulling parameters off of a stack, the
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Ch09_ECOA2e - Chapter 9 Alternative Architectures Chapter 9...

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