fetchExecuteTinyMachine - COP 3269 Computer Architectura...

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COP 3269 Computer Architectura Euripides Montagne University of Central Florida (Fall 2009)
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Eurípides Montagne University of Central Florida 2 Instruction Cycle in the Tiny Computer
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Eurípides Montagne University of Central Florida 3 Outline 1. The structure of a tiny computer. 2. A program as an isolated system. 3. The instruction format. 4. Assembly language.
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Eurípides Montagne University of Central Florida 4 Von-Neumann Machine (VN) PC MAR A MDR OP ADDRESS MEMORY A L U Decoder IR
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Eurípides Montagne University of Central Florida 5 Instruction Cycle The Instruction Cycle , or Machine Cycle, in the Von-Neumann Machine (VN) is composed of 2 steps: 1. Fetch Cycle: Instruction is retrieved from memory. 2. Execution Cycle: Instruction is executed . A simple Hardware Description Language will be used in order to understand how instructions are executed in VN.
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Eurípides Montagne University of Central Florida 6 Definitions Program Counter (PC) is a register that holds the address of the next instruction to be executed. Memory Address Register (MAR) is a register used to store the address to a specific memory location in Main Storage so that data can be written to or read from that location. Main Storage (MEM) is used to store programs and data. Random Access Memory (RAM) is a implementation of MEM.
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Eurípides Montagne University of Central Florida 7 Definitions Memory Data Register (MDR) is a register used to store data that is being sent to or received from the MEM. The data that it stores can either be in the form of instructions or simple data such as an integer. Instruction Register (IR) is a register that stores the instruction to be executed by the processor.
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Eurípides Montagne University of Central Florida 8 Definition Arithmetic Logic Unit (ALU) is used to execute mathematical instructions such as ADD or SUB. DECODER is a circuit that decides which instruction the processor will execute. For example, It takes the instruction op-code from the IR as input and outputs a signal to the ALU to control the execution of the ADD instruction. Accumulator (A) is used to store data to be used as input to the ALU.
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Eurípides Montagne University of Central Florida 9 Fetch-Execute Cycle In the VN, the Instruction Cycle is defined by the following loop: Fetch Execute In order to fully explain the Fetch Cycle we need to study the details of the VN data flow. The data flow consists of 4 steps.
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Eurípides Montagne University of Central Florida 10 Data Movement 1 Given registers PC and MAR, the transfer of the contents of PC into MAR is indicated as: MAR PC A PC MAR MDR OP ADDRESS MEMORY A L U Decoder
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University of Central Florida 11 Data Movement 2 To transfer information from a memory location to the register MDR, we use: MDR MEM[MAR] The address of the memory location has been stored previously into the MAR register PC MAR MDR OP ADDRESS MEMORY(MEM) A L U Decoder A MEM[MAR]
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This note was uploaded on 06/13/2011 for the course CGS 3269 taught by Professor Staff during the Spring '08 term at University of Central Florida.

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fetchExecuteTinyMachine - COP 3269 Computer Architectura...

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