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HW9soln - PHYS3360/AEP3630 Electronic Circuits Spring 2011...

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PHYS3360/AEP3630 Electronic Circuits, Spring 2011, HW9 Solutions 1 Sequential Logic Solutions 1. We will assume a positive-edge-triggered JK flip-flop with PRESET and CLEAR available to us. Actual logic corresponding to this case would be 7470 (positive-edge-triggered dual JK flip- flops). The corresponding spec. sheets are available on the course’s web-site (under Tutorials & Links). PRESET (PR) and CLEAR (CLR) asynchronously set the values of Q and Q regardless of clock, J or K inputs. More precisely, having PR ���� = 0 and CLR ����� = 1 , sets Q = 1 and Q = 0 , and PR ���� = 1 and CLR ����� = 0 produces Q = 0 and Q = 1 . Refer to the corresponding table in the Lab Manual (Table 9.4 on page 224). Table 9.4 is the truth table for D flip-flop (7474 equivalent). The action of PRESET and CLEAR will be identical for JK and D flip-flops. When both PR ���� = 1 and CLR ����� = 1 either flip-flop operates normally in the edge-triggered mode (clock transition ). Finally, setting both PR ���� = 0 and CLR ����� = 0 results in a nonstable configuration and should be
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