VHDL Example - VHDL Examples Subra Ganesan Reference Professor Haskells Notes Digital design with VHDL book by Vranesic n-line 2-to-1 Multiplexer

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VHDL Examples Subra Ganesan Reference: Professor Haskell’s Notes, Digital design with VHDL book by Vranesic
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n-line 2-to-1 Multiplexer n-line 2 x 1 MUX a(n-1:0) b(n-1:0) y(n-1:0) sel sel y 0 a 1 b 2
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library use entity generic port ( a: b: y: ); end mux2g; An n-line 2 x 1 MUX a(n-1:0) y(n-1:0) n-line 2 x 1 3
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library IEEE; use IEEE.std_logic_1164. all ; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; Entity Each entity must begin with these library and use statements port statement defines inputs and outputs generic statement defines width of bus 4
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library IEEE; use IEEE.std_logic_1164. all ; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; Entity Mode: in or out Data type: STD_LOGIC, STD_LOGIC_VECTOR(width-1 downto 0); 5
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Standard Logic type std_ulogic is ( ‘U’, -- Uninitialized ‘X’ -- Forcing unknown ‘0’ -- Forcing zero ‘1’ -- Forcing one ‘Z’ -- High impedance ‘W’ -- Weak unknown ‘L’ -- Weak zero ‘H’ -- Weak one ‘-’); -- Don’t care library IEEE; use IEEE.std_logic_1164. all ; 6
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Standard Logic Type std_ulogic is unresolved. Resolved signals provide a mechanism for handling the problem of multiple output signals connected to one signal. subtype std_logic is resolved std_ulogic; 7
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architecture mux2g_arch of mux2g is begin mux2_1: process (a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if ; end process mux2_1; end mux2g_arch; Architecture a(n-1:0) b(n-1:0) y(n-1:0) sel n-line 2 x 1 MUX Note: <= is signal assignment 8
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architecture mux2g_arch of mux2g is begin mux2_1: process (a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if ; end process mux2_1; end mux2g_arch; Architecture entity name process sensitivity list Sequential statements ( if… then…else ) must be in a process Note begin…end in process Note begin…end in architecture 9
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library IEEE; use IEEE.STD_LOGIC_1164. all ; use IEEE.std_logic_unsigned. all ; entity Lab1 is port ( SW : in STD_LOGIC_VECTOR(7 downto 0); BTN0 : in STD_LOGIC; LD : out STD_LOGIC_VECTOR(3 downto 0) ); end Lab1; 4-line 2-to-1 MUX a b y sel SW(7:4) SW(3:0) BTN0 LD(3:0) Top-level design for Lab 1 10
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architecture Lab1_arch of Lab1 is component mux2g generic ( width : POSITIVE); port ( a : in std_logic_vector((width-1) downto 0); b : in std_logic_vector((width-1) downto 0); sel : in std_logic; y : out std_logic_vector((width-1) downto 0)); end component ; constant bus_width: integer := 4; begin mux2: mux2g generic map(width => bus_width) port map (a => SW(7 downto 4),b => SW(3 downto 0), sel => BTN0, y => LD); end Lab1_arch; 4-line 2-to-1 MUX a b y sel SW(7:4) SW(3:0) BTN0 LD(3:0) 11
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Example of case statement architecture mux4g_arch of mux4g is begin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case ; end process ; end mux4g_arch; Must include ALL possibilities in case statement Note implies operator => Sel y “00” a “01” b “10” c “11” d 12
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7-Segment Display
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This note was uploaded on 06/13/2011 for the course GOV 310L taught by Professor Kieth during the Spring '07 term at University of Texas at Austin.

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VHDL Example - VHDL Examples Subra Ganesan Reference Professor Haskells Notes Digital design with VHDL book by Vranesic n-line 2-to-1 Multiplexer

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