Allen and Holberg - CMOS Analog Circuit Design

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Unformatted text preview: Allen and Holberg - CMOS Analog Circuit Design I. INTRODUCTION Contents I.1 Introduction I.2 Analog Integrated Circuit Design I.3 Technology Overview I.4 Notation I.5 Analog Circuit Analysis Techniques Page I.0-1 Allen and Holberg - CMOS Analog Circuit Design Organization Chapter 10 D/A and A/D Converters Chapter 11 Analog Systems SYSTEMS Chapter 7 CMOS Comparators Chapter 8 Simple CMOS Opamps Chapter 9 High Performance Opamps COMPLEX CIRCUITS Chapter 5 CMOS Subcircuits Chapter 6 CMOS Amplifiers SIMPLE Chapter 2 CMOS Technology Chapter 3 CMOS Device Modeling DEVICES Introduction Chapter 4 Device Characterization Page I.0-2 Allen and Holberg - CMOS Analog Circuit Design Page I.2-1 I.1 - INTRODUCTION GLOBAL OBJECTIVES • Teach the analysis, modeling, simulation, and design of analog circuits implemented in CMOS technology. • Emphasis will be on the design methodology and a hierarchical approach to the subject. SPECIFIC OBJECTIVES 1. Present an overall, uniform viewpoint of CMOS analog circuit design. 2. Achieve an understanding of analog circuit design. • Hand calculations using simple models • Emphasis on insight • Simulation to provide second-order design resolution 3. Present a hierarchical approach. • Sub-blocks → Blocks → Circuits → Systems 4. Examples to illustrate the concepts. Allen and Holberg - CMOS Analog Circuit Design Page I.2-1 I.2 ANALOG INTEGRATED CIRCUIT DESIGN ANALOG DESIGN TECHNIQUES VERSUS TIME FILTERS AMPLIFICATION Passive RLC circuits Open-loop amplifiers 1935-1950 Active-RC Filters Requires precise definition of time constants (RC products) Feedback Amplifiers Requires precise definition of passive components 1978 Switched Capacitor Filters Requires precise C ratios and clock Switched Capacitor Amplifiers Requires precise C ratios 1983 Continuous Time Filters Time constants are adjustable Continuous Time Amplifiers Component ratios are adjustable 1992 ? Digitally assisted analog circuits ? Allen and Holberg - CMOS Analog Circuit Design Page I.2-2 DISCRETE VS. INTEGRATED ANALOG CIRCUIT DESIGN Activity/Item Discrete Integrated Component Accuracy Well known Poor absolute accuracies Breadboarding? Yes No (kit parts) Fabrication Independent Very Dependent Physical PC layout Layout, verification, and Implementation Parasitics extraction Not Important Must be included in the design Simulation Generally complete Must be considered before the design Schematic capture, Schematic capture, simulation, PC board simulation, extraction, layout Components widely testing is possible CAD Model parameters vary known Testing Model parameters well LVS, layout and routing All possible Active devices, capacitors, and resistors Allen and Holberg - CMOS Analog Circuit Design Page I.2-3 THE ANALOG IC DESIGN PROCESS Conception of the idea Definition of the design Comparison with design specifications Implementation Simulation Physical Definition Physical Verification Parasitic Extraction Fabrication Testing and Verification Product Comparison with design specifications Allen and Holberg - CMOS Analog Circuit Design Page I.2-4 COMPARISON OF ANALOG AND DIGITAL CIRCUITS Analog Circuits Digital Circuits are discontinuous in Signals are continuous in amplitude Signal and can be continuous or discrete in amplitude and time - binary signals have two amplitude states time Designed at the circuit level Designed at the systems level Components must have a continuum Component have fixed values of values Customized Standard CAD tools are difficult to apply CAD tools have been extremely successful Requires precision modeling Timing models only Performance optimized Programmable by software Irregular block Regular blocks Difficult to route automatically Easy to route automatically Dynamic range limited by power Dynamic range unlimited supplies and noise (and linearity) Allen and Holberg - CMOS Analog Circuit Design Page I.3-1 I.3 TECHNOLOGY OVERVIEW BANDWIDTHS OF SIGNALS USED IN SIGNAL PROCESSING APPLICATIONS Video Acoustic imaging Seismic Radar Sonar Audio AM-FM radio, TV Telecommunications 1 10 100 1k 10k 100k 1M 10M 100M Signal Frequency (Hz) Microwave 1G Signal frequency used in signal processing applications. 10G 100G Allen and Holberg - CMOS Analog Circuit Design Page I.3-2 BANDWIDTHS THAT CAN BE PROCESSED BY PRESENTDAY TECHNOLOGIES BiCMOS Bipolar analog Bipolar digital logic MOS digital logic MOS analog Optical GaAs 1 10 100 1k 10k 100k 1M 10M 100M Signal Frequency (Hz) 1G 10G Frequencies that can be processed by present-day technologies. 100G Allen and Holberg - CMOS Analog Circuit Design Page I.3-3 CLASSIFICATION OF SILICON TECHNOLOGY Silicon IC Technologies Bipolar Junction Isolated Dielectric Isolated Bipolar/MOS CMOS Aluminum gate MOS PMOS (Aluminum Gate) Silicon gate NMOS Aluminum gate Silicon gate Allen and Holberg - CMOS Analog Circuit Design Page I.3-4 BIPOLAR VS. MOS TRANSISTORS CATEGORY BIPOLAR CMOS Turn-on Voltage 0.5-0.6 V 0.8-1 V Saturation Voltage 0.2-0.3 V 0.2-0.8 V gm at 100 µA 4 mS 0.4 mS (W=10L) Analog Switch Implementation Offsets, asymmetric Good Power Dissipation Moderate to high Low but can be large Speed Faster Fast Compatible Capacitors Voltage dependent Good AC Performance Dependence DC variables only DC variables and geometry Number of Terminals 3 4 Noise (1/f) Good Poor Noise Thermal OK OK Offset Voltage < 1 mV 5-10 mV Allen and Holberg - CMOS Analog Circuit Design Page I.3-5 WHY CMOS??? CMOS is nearly ideal for mixed-signal designs: • Dense digital logic • High-performance analog DIGITAL ANALOG MIXED-SIGNAL IC Allen and Holberg - CMOS Analog Circuit Design I.4 NOTATION SYMBOLS FOR TRANSISTORS Drain Gate Drain Bulk Gate Source Source/bulk n-channel, enhance- n-channel, enhancement, bulk at most ment, VBS ≠ 0 negative supply Drain Gate Drain Bulk Gate Source Source/bulk p-channel, enhance- p-channel, enhancement, bulk at most ment, VBS ≠ 0 positive supply Page I.4-1 Allen and Holberg - CMOS Analog Circuit Design SYMBOLS FOR CIRCUIT ELEMENTS Operational Amplifier/Amplifier/OTA + - I V + + G mV1 AvV1 V1 V1 - - VCVS VCCS I1 I1 Rm I 1 CCVS Ai I 1 CCCS Page I.4-2 Allen and Holberg - CMOS Analog Circuit Design Page I.4-3 Notation for signals Id id ID iD time Allen and Holberg - CMOS Analog Circuit Design II. CMOS TECHNOLOGY Contents II.1 Basic Fabrication Processes II.2 CMOS Technology II.3 PN Junction II.4 MOS Transistor II.5 Passive Components II.6 Latchup Protection II.7 ESD Protection II.8 Geometrical Considerations Page II.0-1 Allen and Holberg - CMOS Analog Circuit Design Perspective Chapter 10 D/A and A/D Converters Chapter 11 Analog Systems SYSTEMS Chapter 7 CMOS Comparators Chapter 8 Simple CMOS Opamps Chapter 9 High Performance Opamps COMPLEX CIRCUITS Chapter 5 CMOS Subcircuits Chapter 6 CMOS Amplifiers SIMPLE Chapter 2 CMOS Technology DEVICES Chapter 3 CMOS Device Modeling Chapter 4 Device Characterization Page II.0-2 Allen and Holberg - CMOS Analog Circuit Design Page II.0-3 OBJECTIVE • Provide an understanding of CMOS technology sufficient to enhance circuit design. • Characterize passive components compatible with basic technologies. • Provide a background for modeling at the circuit level. • Understand the limits and constraints introduced by technology. Allen and Holberg - CMOS Analog Circuit Design Page II.1-1 II.1 - BASIC FABRICATION PROCESSES BASIC FABRTICATION PROCESSES Basic Steps • Oxide growth • Thermal diffusion • Ion implantation • Deposition • Etching Photolithography Means by which the above steps are applied to selected areas of the silicon wafer. Silicon wafer 0.5-0.8 mm 125-200 mm n-type: 3-5 Ω -cm p-type: 14-16 Ω -cm Allen and Holberg - CMOS Analog Circuit Design Page II.1-2 Oxidation The process of growing a layer of silicon dioxide (SiO2)on the surface of a silicon wafer. Original Si surface tox SiO 2 0.44 tox Si substrate Uses: • Provide isolation between two layers • Protect underlying material from contamination • Very thin oxides (100 to 1000 Å) are grown using dry-oxidation techniques. Thicker oxides (>1000 Å) are grown using wet oxidation techniques. Allen and Holberg - CMOS Analog Circuit Design Page II.1-3 Diffusion Movement of impurity atoms at the surface of the silicon into the bulk of the silicon - from higher concentration to lower concentration. High Concentration Low Concentration Diffusion typically done at high temperatures: 800 to 1400 °C. Infinite-source diffusion: N0 ERFC t1<t2<t3 N(x) NB t1 t3 t2 Depth (x) Finite-source diffusion: N0 Gaussian t1<t2<t3 N(x) NB t1 t2 Depth (x) t3 Allen and Holberg - CMOS Analog Circuit Design Page II.1-4 Ion Implantation Ion implantation is the process by which impurity ions are accelerated to a high velocity and physically lodged into the target. Path of impurity atom Fixed atoms Impurity final resting place • Anneal required to activate the impurity atoms and repair physical damage to the crystal lattice. This step is done at 500 to 800 °C. • Lower temperature process compared to diffusion. • Can implant through surface layers, thus it is useful for field-threshold adjustment. • Unique doping provile available with buried concentration peak. Concentration peak N(x) NB 0 Depth (x) Allen and Holberg - CMOS Analog Circuit Design Page II.1-5 Deposition Deposition is the means by which various materials are deposited on the silicon wafer. Examples: • Silicon nitride (Si3N4) • Silicon dioxide (SiO2) • Aluminum • Polysilicon There are various ways to deposit a meterial on a substrate: • Chemical-vapor deposition (CVD) • Low-pressure chemical-vapor deposition (LPCVD) • Plasma-assisted chemical-vapor deposition (PECVD) • Sputter deposition Materials deposited using these techniques cover the entire wafer. Allen and Holberg - CMOS Analog Circuit Design Page II.1-6 Etching Etching is the process of selectively removing a layer of material. When etching is performed, the etchant may remove portions or all of: • the desired material • the underlying layer • the masking layer Important considerations: • Anisotropy of the etch lateral etch rate A = 1 - vertical etch rate • Selectivity of the etch (film toomask, and film to substrate) f ilm etch rate Sfilm-mask = mask etch rate Desire perfect anisotropy (A=1) and invinite selectivity. There are basically two types of etches: • Wet etch, uses chemicals • Dry etch, uses chemically active ionized gasses. a Mask Film c b Underlying layer Allen and Holberg - CMOS Analog Circuit Design Page II.1-7 Photolithography Components • Photoresist material • Photomask • Material to be patterned (e.g., SiO2) Positive photoresistAreas exposed to UV light are soluble in the developer Negative photoresistAreas not exposed to UV light are soluble in the developer Steps: 1. Apply photoresist 2. Soft bake 3. Expose the photoresist to UV light through photomask 4. Develop (remove unwanted photoresist) 5. Hard bake 6. Etch the exposed layer 7. Remove photoresist Allen and Holberg - CMOS Analog Circuit Design Photomask UV Light Photomask Photoresist Polysilicon Page II.1-8 Allen and Holberg - CMOS Analog Circuit Design Page II.1-9 Polysilicon Photoresist Photoresist Polysilicon Polysilicon Positive Photoresist Allen and Holberg - CMOS Analog Circuit Design Page II.2-1 II.2 - CMOS TECHNOLOGY TWIN-WELL CMOS TECHNOLOGY Features • Two layers of metal connections, both of them of high quality due to a planarization step. • Optimal threshold voltages of both p-channel and n-channel transistors • Lightly doped drain (LDD) transistors prevent hot-electron effects. • Good latchup protection Allen and Holberg - CMOS Analog Circuit Design Page II.2-2 n-well implant SiO2 Photoresist Photoresist p- substrate (a) Si3N4 SiO2 n-well p- substrate (b) n- field implant Photoresist Photoresist Si3N4 n-well p- substrate (c) p- field implant Si3N4 Photoresist n-well p- substrate (d) Figure 2.1-5 The major CMOS process steps. Pad oxide (SiO2) Allen and Holberg - CMOS Analog Circuit Design Page II.2-3 Si3N4 FOX FOX n-well p- substrate (e) Polysilicon FOX FOX n-well p- substrate (f) SiO2 spacer Polysilicon Photoresist FOX FOX n-well p- substrate (g) n+ S/D implant Polysilicon Photoresist FOX FOX n-well p- substrate (h) Figure 2.1-5 The major CMOS process steps (cont'd). Allen and Holberg - CMOS Analog Circuit Design Page II.2-4 n- S/D LDD implant Polysilicon Photoresist FOX FOX n-well p- substrate (i) LDD Diffusion Polysilicon FOX FOX n-well p- substrate (j) n+ Diffusion p+ Diffusion Polysilicon FOX FOX n-well p- substrate (k) n+ Diffusion p+ Diffusion Polysilicon BPSG FOX FOX n-well p- substrate (l) Figure 2.1-5 The major CMOS process steps (cont'd). Allen and Holberg - CMOS Analog Circuit Design CVD oxide, Spin-on glass (SOG) Page II.2-5 Metal 1 BPSG FOX FOX n-well p- substrate (m) Metal 2 Metal 1 BPSG FOX FOX n-well p- substrate (n) Metal 2 Metal 1 Passivation protection layer BPSG FOX FOX n-well p- substrate (o) Figure 2.1-5 The major CMOS process steps (cont'd). Allen and Holberg - CMOS Analog Circuit Design Page II.2-6 Silicide/Salicide Purpose • Reduce interconnect resistance, Polysilicide Polysilicide Metal Silicide FOX FOX (b) (a) Figure 2.1-6 (a) Polycice structure and (b) Salicide structure. Allen and Holberg - CMOS Analog Circuit Design Page II.3-1 II.3 - PN JUNCTION CONCEPT Metallurgical Junction n-type semiconductor p-type semiconductor iD +vD Depletion region n-type semiconductor p-type semiconductor iD v + Dxd xp 0 xn x 1. Doped atoms near the metallurgical junction lose their free carriers by diffusion. 2. As these fixed atoms lose their free carriers, they build up an electric field which opposes the diffusion mechanism. 3. Equilibrium conditions are reached when: Current due to diffusion = Current due to electric field Allen and Holberg - CMOS Analog Circuit Design Page II.3-2 PN JUNCTION CHARACTERIZATION xd xp xn p-type semiconductor n-type semiconductor iD +vD - Impurity concentration ( cm-3 ) ND x 0 -NA Depletion charge concentration ( cm-3 ) qND xp 0 x xn -qNA Electric Field (V/cm) x Eo Potential (V) φo− v D x xd Allen and Holberg - CMOS Analog Circuit Design Page II.3-3 SUMMARY OF PN JUNCTION ANALYSIS Barrier potentialφo = k T NAND NAND ln 2 = Vt ln 2 q ni ni Depletion region widthsxn = xp = 2εsi(φo-vD)NA qND(NA+ND) 2εsi(φo-vD)ND qND(NA+ND) x∝ Depletion capacitanceCj = A εsiqNAND 2(NA+ND) 1 φo-vD Breakdown voltageεsi(NA+ND) 2 Emax BV = 2qN N AD = Cj0 φo-vD 1 N Allen and Holberg - CMOS Analog Circuit Design Page II.3-4 SUMMARY - CONTINUED Current-Voltage Relationship vD iD = IsexpV - 1 t Dppno D n n p o where Is = qA L + L p n 25 20 iD 15 Is 10 5 0 -5 -4 -3 -2 -1 0 vD/Vt 1 2 3 4 10 x1016 8 x1016 16 iD 6 x10 Is 4 x1016 2 x1016 0 -40 -30 -20 -10 0 vD/Vt 10 20 30 40 Allen and Holberg - CMOS Analog Circuit Design II.4-1 II.4 - MOS TRANSISTOR ILLUSTRATION Source Gate Drain p+ Ch an n Polysilicon el W id th , W Bulk Fig. 4.3-4 n+ n+ n-channel p-substrate (bulk) Channel Length, L tOX = 200 Angstroms = 0.2x10-7 meters = 0.02 µm TYPES OF TRANSISTORS iD Depletion Mode VT (depletion) Enhancement Mode VT (enhancement) vGS Allen and Holberg - CMOS Analog Circuit Design II.4-2 CMOS TRANSISTOR N-well process p-channel transistor SiO2 p+ FOX n-well W dra in ( n+) L sou rce (n+ ) L dra in ( p+) W n+ sou rce (p+ ) Polysilicon n-channel transistor p- substrate Figure 2.3-1 Physical structure of an n-channel and p-channel transistor in an n-well technology. P-well process • Inverse of the above. Normally, all transistors are enhancement mode. Allen and Holberg - CMOS Analog Circuit Design II.4-3 TRANSISTOR OPERATING POLARTIES Type of Device n-channel, enhancement Polarity of vGS and V T + Polarity of vDS + - p-channel, depletion - + p-channel, enhancement + - n-channel, depletion - SYMBOLS FOR TRANSISTORS Drain Gate Drain Bulk Gate Source Source/bulk n-channel, enhance- n-channel, enhancement, bulk at most ment, VBS ≠ 0 negative supply Drain Gate Drain Bulk Gate Source Source/bulk p-channel, enhance- p-channel, enhancement, bulk at most ment, VBS ≠ 0 positive supply Polarity of vBULK Most negative Most negative Most positive Most positive Allen and Holberg - CMOS Analog Circuit Design II.5-1 II.5 - PASSIVE COMPONENTS C APACITORS εoxA C = tox Polysilicon-Oxide-Channel Capacitor and Polysilicon-Oxide-Polysilicon Capacitor Metal SiO2 Polysilicon top plate Gate SiO2 FOX FOX p+ bottom-plate implant p- substrate (a) Polysilicon top plate Polysilicon bottom plate FOX Inter-poly SiO2 p- substrate (b) Figure 2.4-1 MOS capacitors. (a) Polysilicon-oxide-channel. (b) Polysilicon-oxide-polysilicon. Allen and Holberg - CMOS Analog Circuit Design II.5-2 Metal-Metal and Metal-Metal-Poly Capacitors M3 M2 B M1 T Poly T M3 T M2 M1 B M2 B T B M1 Poly T M2 M1 B Figure 2.4-2 Various ways to implement capacitors using available interconnect layers. M1, M2, and M3 represent the first, second, and third metal layers respectively. Top plate parasitic Cdesired Bottom plate parasitic Figure 2.4-3 A model for the integrated capacitors showing top and bottom plate parasitics. Allen and Holberg - CMOS Analog Circuit Design PROPER LAYOUT OF CAPACITORS • Use “unit” capacitors • Use “common centroid” Want A=2*B Case (a) fails Case (b) succeeds! (a) A1 A2 B (b) A1 B A2 x1 x2 x3 y Figure 2.6-2 Components placed in the presence of a gradient, (a) without commoncentroid layout and (b) with common-centroid layout. II.5-3 Allen and Holberg - CMOS Analog Circuit Design NON-UNIFORM UNDERCUTTING EFFECTS Random edge distortion Large-scale distortion Corner-rounding distortion II.5-4 Allen and Holberg - CMOS Analog Circuit Design II.5-5 VICINITY EFFECT C A B C A B Figure 2.6-1 (a)Illustration of how matching of A and B is disturbed by the presence of C. (b) Improved matching achieved by matching surroundings of A and B Allen and Holberg - CMOS Analog Circuit Design IMPROVED LAYOUT METHODS FOR CAPACITORS Corner clipping: Clip corners Street-effect compensation: II.5-6 Allen and Holberg - CMOS Analog Circuit Design II.5-7 ERRORS IN CAPACITOR RATIOS Let C1 be defined as C1 = C1A + C1P and C2 be defined as C2 = C2A + C2P CXA is the bottom-plate capacitance CXP is the fringe (peripheral) capacitance CXA >> CXP The ratio of C2 to C1 can be expressed as 2P 1 + C2A C2A C1A C1P 1 + C C2 C2A + C2P C1 = C1A + C1P = C1A C2A C2P C1P (C1P)(C2P) ≅ C 1 + C - C - C C 1A 2A 1A 1A 2A C2A C2P C1P ≅ C 1 + C - C 1A 2A 1A Thus best matching is achieved when the area to periphery ratio remains constant. Allen and Holberg - CMOS Analog Circuit Design II.5-8 CAPACITOR PARASITICS Top Plate Top plate parasitic Desired Capacitor Bottom Plate Bottom plate parasitic Parasitic is dependent upon how the capacitor is constructed. Typical capacitor performance (0.8 µ m Technology) Capacitor Type Poly/poly capacitor MOS capacitor MOM capacitor Range of Values Temperature Coefficient 0.8-1.0 fF/µm2 Relative Accuracy 0.05% Absolute Accuracy 50 ppm/ °C Voltage Coefficient 50 ppm/V 2.2-2.5 fF/µm2 0.05% 50 ppm/ °C 50 ppm/V ±10% 0.02-0.03 fF/µm2 1.5% ±10% ±10% Allen and Holberg - CMOS Analog Circuit Design II.5-9 RESISTORS IN CMOS TECHNOLOGY Metal p+ SiO2 FOX FOX n- well p- substrate (a) Metal Polysilicon resistor FOX p- substrate (b) Metal n+ FOX FOX n- well p- substrate (c) Figure 2.4-4 Resistors. (a) Diffused (b) Polysilicon (c) N-well FOX Allen and Holberg - CMOS Analog Circuit Design II.5-10 PASSIVE COMPONENT SUMMARY (0.8 µ m Technology) Component Range of Values Matching Type Accuracy Poly/poly 0.05% 0.8-1.0 fF/µm2 capacitor MOS 0.05% 2.2-2.5 fF/µm2 capacitor MOM 1.5% 0.02-0.03 fF/µm2 capacitor Diffused 0.4% 20-150 Ω/sq. resistor Polysilicide R 2-15 Ω/sq. Poly resistor 0.4% 20-40 Ω/sq. N-well 0.4% 1-2k Ω/sq. resistor Temperature Coefficient Absolute Accuracy 50 ppm/ °C Voltage Coefficient 50ppm/V 50 ppm/ °C 50ppm/V ±10% ±10% ±10% 1500 ppm/ °C 200ppm/V ±35% 1500 ppm/ °C 8000 ppm/ °C 100ppm/V 10k ppm/V ±30% ±40% Allen and Holberg - CMOS Analog Circuit Design II.5-11 BIPOLARS IN CMOS TECHNOLOGY Metal Emitter (p+) Base (n+) FOX FOX FOX WB n- well Collector (p- substrate) Figure 2.5-1 Substrate BJT available from a bulk CMOS process. Depletion regions p Emitter n Base p Collector Carrier concentration ppE nn(x) ppC pn(0) NA npE(0) ND NA pn(x) npE ppC pn(wB) x=0 x=wB Figure 2.5-2 Minority carrier concentrations for a bipolar junction transistor. x Allen and Holberg - CMOS Analog Circuit Design II.6-1 II.6 - LATCHUP S G D=B S G Well tie Substrate tie p+ FOX n+ n+ FOX p+ Q2 Q1 p-substrate VDD D=A p+ RN- FOX n+ n-well RP(a) VDD RN- Q2 A Q1 B RP- (b) Figure 2.5-3 (a) Parasitic lateral NPN and vertical PNP bipolar transistor in CMOS integrated circuits. (b) Equivalent circuit of the SCR formed from the parasitic bipolar transistors. Allen and Holberg - CMOS Analog Circuit Design II.6-2 PREVENTING LATCHUP p-channel transistor n-channel transistor n+ guard bars p+ guard bars VDD VSS FOX n-well p- substrate Figure 2.5-4 Preventing latch-up using guard bars in an n-well technology Allen and Holberg - CMOS Analog Circuit Design II.6-1 II.7 - ESD PROTECTION VDD p+ – n-well diode To internal gates Bonding Pad p+ resistor n+ – substrate diode VSS (a) Metal n+ FOX p+ FOX n-well p-substrate (b) Figure 2.5-5 Electrostatic discharge protection circuitry. (a) Electrical equivalent circuit (b) Implementation in CMOS technology Allen and Holberg - CMOS Analog Circuit Design II.8-1 II.8 - GEOMETRICAL CONSIDERATIONS Design Rules for a Double-Metal, Double-Polysilicon, N-Well, Bulk CMOS Process. Minimum Dimension Resolution (λ) 1. N-Well 1A. width .........................................................................6 1B. spacing .................................................................... 12 2. Active Area (AA) 2A. width .........................................................................4 Spacing to Well 2B. AA-n contained in n-Well.............................................1 2C. AA-n external to n-Well............................................. 10 2D. AA-p contained in n-Well.............................................3 2E. AA-p external to n-Well...............................................4 Spacing to other AA (inside or outside well) 2F. AA to AA (p or n).......................................................3 3. Polysilicon Gate (Capacitor bottom plate) 3A. width..........................................................................2 3B. spacing .......................................................................3 3C. spacing of polysilicon to AA (over field)........................1 3D. extension of gate beyond AA (transistor width dir.) ........2 3E. spacing of gate to edge of AA (transistor length dir.) ......4 4. Polysilicon Capacitor top plate 4A. width..........................................................................2 4B. spacing .......................................................................2 4C. spacing to inside of polysilicon gate (bottom plate)..........2 5. Contacts Allen and Holberg - CMOS Analog Circuit Design II.8-2 5A. size ....................................................................... 2x2 5B. spacing .......................................................................4 5C. spacing to polysilicon gate ............................................2 5D. spacing polysilicon contact to AA ..................................2 5E. metal overlap of contact ...............................................1 5F. AA overlap of contact ..................................................2 5G. polysilicon overlap of contact........................................2 5H. capacitor top plate overlap of contact.............................2 6. Metal-1 6A. width..........................................................................3 6B. spacing .......................................................................3 7. Via 7A. size ....................................................................... 3x3 7B. spacing .......................................................................4 7C. enclosure by Metal-1....................................................1 7D. enclosure by Metal-2....................................................1 8. Metal-2 8A. width..........................................................................4 8B. spacing .......................................................................3 Bonding Pad 8C. spacing to AA............................................................ 24 8D. spacing to metal circuitry ........................................... 24 8E. spacing to polysilicon gate .......................................... 24 Allen and Holberg - CMOS Analog Circuit Design 9. II.8-3 Passivation Opening (Pad) 9A. bonding-pad opening ..............................100µm x 100 µm 9B. bonding-pad opening enclosed by Metal-2 ......................8 9C. bonding-pad opening to pad opening space ................... 40 Note: For a P-Well process, exchange p and n in all instances. Allen and Holberg - CMOS Analog Circuit Design II.8-4 1B 1A 2E 2B 2A 2F 2C 2D 3C 3A 3E 3D 3B Figure 2.6-8(a) Illustration of the design rules 1-3 of Table 2.6-1. Allen and Holberg - CMOS Analog Circuit Design 4C II.8-5 4B 4A 5C 5A 5B 5D 5E 5F 5G 5H Figure 2.6-8(b) Illustration of the design rules 4-5 of Table 2.6-1. Allen and Holberg - CMOS Analog Circuit Design II.8-6 7A 7B 6B 7C 6A 7D 8A 8B 9B 9A 9C N-WELL N-AA P-AA POLYSILICON CAPACITOR POLYSILICON GATE METAL-1 METAL-2 PASSIVATION CONTACT Figure 2.6-8(c) Illustration of the design rules 6-9 of Table 2.6-1. VIA Allen and Holberg - CMOS Analog Circuit Design II.8-7 Transistor Layout Metal FOX Active area drain/source FOX Polysilicon gate L Contact Cut W Active area drain/source Metal 1 Figure 2.6-3 Example layout of an MOS transistor showing top view and side view at the cut line indicated. Allen and Holberg - CMOS Analog Circuit Design II.8-8 SYMMETRIC VERSUS PHOTOLITHOGRAPHIC INVARIANT (a) (b) Figure 2.6-4 Example layout of MOS transistors using (a) mirror symmetry, and (b) photolithographic invariance. PLI IS BETTER Allen and Holberg - CMOS Analog Circuit Design II.8-9 Resistor Layout Metal FOX FOX Substrate Active area (diffusion) Contact Active area or Polysilicon W Cut L Metal 1 (a) Diffusion or polysilicon resistor Metal FOX FOX FOX Substrate Active area (diffusion) Well diffusion Active area Well diffusion W Contact Cut L Metal 1 (b) Well resistor Figure 2.6-5 Example layout of (a) diffusion or polysilicon resistor and (b) Well resistor along with their respective side views at the cut line indicated. Allen and Holberg - CMOS Analog Circuit Design II.8-10 Capacitor Layout Polysilicon 2 Metal FOX Substrate Polysilicon gate Polysilicon gate Polysilicon 2 Cut Metal 1 (a) Metal 3 Metal 2 Metal 1 FOX Substrate Metal 3 Metal 1 Metal 2 Metal 3 Via 2 Via 2 Metal 2 Cut Via 1 Metal 1 (b) Figure 2.6-7 Example layout of (a) double-polysilicon capacitor, and (b) triple-level metal capacitor along with their respective side views at the cut line indicated. Allen and Holberg - CMOS Analog Circuit Design III. CMOS MODELS Contents III.1 Simple MOS large-signal model Strong inversion Weak inversion III.2 Capacitance model III.3 Small-signal MOS model III.4 SPICE Level-3 model Perspective Chapter 10 D/A and A/D Converters Chapter 11 Analog Systems SYSTEMS Chapter 7 CMOS Comparators Chapter 8 Simple CMOS OP AMPS Chapter 9 High Performance OTA's COMPLEX CIRCUITS Chapter 5 CMOS Subcircuits Chapter 6 CMOS Amplifiers SIMPLE Chapter 2 CMOS Technology DEVICES Chapter 3 CMOS Device Modeling Chapter 4 Device Characterization Page III.0-1 Allen and Holberg - CMOS Analog Circuit Design Page III.1-1 III.1 - MODELING OF CMOS ANALOG CIRCUITS Objective 1. Hand calculations and design of analog CMOS circuits. 2. Efficiently and accurately simulate analog CMOS circuits. Large Signal Model The large signal model is nonlinear and is used to solve for the dc values of the device currents given the device voltages. The large signal models for SPICE: Basic drain current models 1. Level 1 - Shichman-Hodges (VT, K', γ, λ, φ, and NSUB) 2. Level 2 - Geometry-based analytical model. Takes into account second-order effects (varying channel charge, short-channel, weak inversion, varying surface mobility, etc.) 3. Level 3 - Semi-empirical short-channel model 4. Level 4 - BSIM model. Based on automatically generated parameters from a process characterization. Good weak-strong inversion transition. Basic model auxilliary parameters include capacitance [Meyer and Ward-Dutton (charge-conservative)], bulk resistances, depletion regions, etc.. Small Signal Model Based on the linearization of any of the above large signal models. Simulator Software SPICE2 - Generic SPICE available from UC Berkeley (FORTRAN) SPICE3 - Generic SPICE available from UC Berkeley (C) *SPICE*- Every other SPICE simulator! Allen and Holberg - CMOS Analog Circuit Design Page III.1-2 Transconductance Characteristics of NMOS when VDS = 0.1V vGS ≤ VT: + v GS = VT - Source and bulk iD Gate Drain + iD VDS - =0.1V 0 0 p substrate (bulk) VT 2VT 3VT v GS VT 2VT 3VT v GS VT 2VT 3VT v GS vGS = 2VT: Source and bulk + v GS = 2VT - iD Gate Drain + VDS =0.1V - iD 0 0 p substrate (bulk) vGS = 3VT: Source and bulk + v GS = 3VT- iD Gate Drain + iD VDS - =0.1V 0 p substrate (bulk) 0 Allen and Holberg - CMOS Analog Circuit Design Page III.1-3 Output Characteristics of NMOS for VGS = 2VT vDS = 0V: Source and bulk VGS + = 2VT - + iD Gate - Drain iD v DS = 0V 0 p substrate (bulk) 0 0.5VT VT v DS vDS = 0.5VT: Source and bulk VGS + = 2VT - + iD Gate - Drain v DS = i D 0.5 VT 0 p substrate (bulk) 0 0.5VT VT v DS vDS = VT: Source and bulk VGS + = 2VT - p substrate (bulk) iD Gate Drain x + - v DS = VT iD 0 0.5V T VT vDS Allen and Holberg - CMOS Analog Circuit Design Page III.1-4 Output Characteristics of NMOS when vDS = 4VT vGS = VT: Source and bulk v GS = VT + - iD Gate Drain + v = iD DS 4VT - vDS(sat) 0 0 VT 2VT 3VT 4VT v DS p substrate (bulk) vGS = 2VT: Source and bulk + v GS = 2VT - iD Gate Drain + v = iD DS - 4VT vDS(sat) 0 0 VT 2VT 3VT 4VT v DS p substrate (bulk) vGS = 3VT: Source and bulk v GS = 3VT + - iD Gate Drain + v = iD DS 4VT - vDS(sat) 0 p substrate (bulk) 0 VT 2VT 3VT 4VT v DS Allen and Holberg - CMOS Analog Circuit Design Page III.1-5 Output Characteristics of an n-channel MOSFET 2.0 Output Characteristics of a n-channel MOSFET .MODEL MN1K100 NMOS VTO=1 KP=200U LAMBDA=0.01 .DC VDS 0 10 0.5 VGS 1 5 1 VGS=5V MOSFET1 2 1 0 0 MN1K100 .PRINT DC ID(MOSFET1) VGS 1 0 VDS 2 0 .PROBE .END 1.5 iD (mA) VGS=4V 1.0 0.5 VGS=3V 0 VGS=2V VGS=1V 0 2 4 vDS (V) 6 8 10 Transconductance Characteristics of an n-channel MOSFET 2.0 Transconductance Characteristics of a n-channel MOSFET .MODEL MN1K100 NMOS VTO=1 KP=200U LAMBDA=0.01 .DC VGS 0 5 0.5 VDS 2 8 2 MOSFET1 2 1 0 0 MN1K100 .PRINT DC ID(MOSFET1) VGS 1 0 VDS 2 0 .PROBE .END 1.5 iD (mA) VDS=8V VDS=6V VDS=4V VDS=2V 1.0 0.5 0 0 1 2 3 vGS(V) 4 5 Allen and Holberg - CMOS Analog Circuit Design Page III.1-6 SIMPLIFIED SAH MODEL DERIVATION Model+ vGS - p- n+ Source v(y) 0 + v - DS iD dy y y+dy n+ Drain L y Derivation• Let the charge per unit area in the channel inversion layer be QI(y) = C ox[vGS − v(y) − VT] (coulombs/cm2) • Define sheet conductivity of the inversion layer per square as 1 cm2 coulombs amps σS = µoQI(y) v·s cm2 = volt = Ω/sq. • Ohm's Law for current in a sheet is iD dv JS = = σSE y = σS W dy . Rewriting Ohm's Law gives, iD iDdy dv = σ W dy = Q (y)W µo I S where dv is the voltage drop along the channel in the direction of y. Rewriting as iD dy = WµoQI(y)dv and integrating along the channel for 0 to L gives vDS L vDS ⌠iDdy = ⌡WµoQI(y)dv = ⌠WµoCox[vGS−v(y)−VT] dv ⌠ ⌡ ⌡ 0 0 0 After integrating and evaluating the limits 2 vDS WµoCox iD = (vGS−VT)vDS − 2 L Allen and Holberg - CMOS Analog Circuit Design Page III.1-7 ILLUSTRATION OF THE SAH EQUATION Plotting the Sah equation as iD vs. vDS results in iD vDS = vGS - VT Non-Sat Region Saturation Region Increasing values of vGS vDS Define vDS(sat) = vGS − VT Regions of Operation of the MOS Transistor 1.) Cutoff Region: iD = 0, vGS − VT < 0 (Ignores subthreshold currents) 2.) Non-saturation Region iD = µCoxW 2L 2(vGS − VT) − v DS vDS , 0 < vDS < vGS − VT 3.) Saturation Region iD = µCoxW 2 2L (vGS − VT) , 0 < vGS − VT < vDS Allen and Holberg - CMOS Analog Circuit Design Page III.1-8 SAH MODEL ADJUSTMENT TO INCLUDE EFFECTS OF VDS ON VT From the previous derivation: vDS vDS L ⌠ iD dy = ⌠ WµoQI(y)dy = ⌠ WµoCox[vGS − v(y) − V T]dv ⌡ ⌡ ⌡ 0 0 0 Assume that the threshld voltage varies across the channel in the following way: VT(y) = VT + ∆ v(y) where V T is the value of the threshold voltage at the source end of the channel. Integrating the above gives, v WµoCox v2(y) DS (vGS−VT)v(y) − (1+∆ ) iD = L 2 0 or iD = WµoCox v2DS (vGS−VT)vDS − (1+∆ ) L 2 To find vDS(sat), set the derivative of iD with respect to vDS equal to zero and solve for vDS = vDS(sat) to get, vDS(sat) = vGS − VT 1+∆ Therefore, in the saturation region, the drain current is iD = 2 WµoCox vGS − V T 2(1+ ∆ )L Allen and Holberg - CMOS Analog Circuit Design Page III.1-9 EFFECTS OF BACK GATE (BULK-SOURCE) Bulk-Source (vBS) influence on the transconductance characteristicsiD Decreasing values of bulk-source voltage VBS = 0 vDS ≥ vGS - VT vGS VT0 VT1 VT2 VT3 In general, the simple model incorporates the bulk effect into V T by the following empirically developed equationVT(V BS) =V T0 + γ 2|φf| + |vBS| − γ 2|φf| Allen and Holberg - CMOS Analog Circuit Design Page III.1-10 EFFECTS OF THE BACK GATE - CONTINUED IllustrationVSB0 = 0V: VSB0 =0V + Source Bulk Drain VDS>0 Poly n+ p+ p- Gate VGS>VT n+ Substrate/Bulk VSB1>0V: VSB1 + Gate VGS>VT Source Bulk Poly n+ p+ p- Drain VDS>0 n+ Substrate/Bulk VSB2 > VSB1: - VSB2 Source Bulk p+ p- Gate VGS>VT + Substrate/Bulk Drain VDS>0 Poly n+ n+ Allen and Holberg - CMOS Analog Circuit Design Page III.1-11 SAH MODEL INCLUDING CHANNEL LENGTH MODULATION N-channel reference convention: D iD G + + + vGS B vDS vBS - -S Non-saturationiD = WµoCox vDS2 (vGS − V T)vDS − L 2 SaturationWµoCox vDS(sat)2 (vGS − V T)vDS(sat) − (1 + λvDS) iD = L 2 = WµoCox 2 2L (vGS − VT) (1 + λvDS) where: µo = zero field mobility (cm2/volt·sec) Cox = gate oxide capacitance per unit area (F/cm2) λ = channel-length modulation parameter (volts-1) VT = VT0 + γ 2|φf| + |vBS| − 2|φf| VT0 = zero bias threshold voltage γ = bulk threshold parameter (volts1/2) 2|φf| = strong inversion surface potential (volts) When solving for p-channel devices, negate all voltages and use the nchannel model with p-channel parameters and negate the current. Also negate VT0 of the p device. Allen and Holberg - CMOS Analog Circuit Design Page III.1-12 OUTPUT CHARACTERISTICS OF THE MOS TRANSISTOR iD /ID0 vDS = vGS - VT 1.0 Non-Sat Region Saturation Region 0.75 Channel modulation effects 0.5 0.25 Cutoff Region 0 0 0.5 1.0 1.5 Notation: W W ß = K' = (µoCox) L L Note: µoCox = K' 2.0 vGS -VT = 1.0 VGS0 - VT vGS-VT = 0.867 VGS0 - VT vGS-VT = 0.707 VGS0 - VT vGS-VT = 0.5 VGS0 - VT vGS-VT = 0 VGS0 - VT vDS VGS0 - VT 2.5 Allen and Holberg - CMOS Analog Circuit Design Page III.1-13 GRAPHICAL INTERPRETATION OF λ Assume the MOS is transistor is saturatedµCoxW ∴ iD = 2L (vGS − VT) 2(1 + λvDS) Define iD(0) = iD when vDS = 0V. ∴ iD(0) = µCoxW 2 2L (vGS − VT) Now, iD = iD(0) [1+λvDS] = iD(0) + λiD(0) vDS or 1 1 vDS = iD − λ λiD (0) Matching with y = mx + b gives vDS 1 1 λ iD(0) iD iD(0) -1 λ or iD iD3(0) iD2(0) iD1(0) -1 λ VGS3 VGS2 VGS1 vDS Allen and Holberg - CMOS Analog Circuit Design Page III.1-14 SPICE LEVEL 1 MODEL PARAMETERS FOR A TYPICAL BULK CMOS PROCESS (0.8µm) Model Parameter VT0 K' Parameter Description Typical Parameter Value NMOS PMOS Units ThresholdVoltage forVBS = 0V 0.75±0.15 − 0.85±0.15 Volts Transconductance Parameter 110±10% 50±10% µA/V2 0.4 0.57 V 0.04 (L=1 µm) 0.01 (L=2 µm) 0.05 (L = 1 µm) 0.01 (L = 2 µm) V-1 0.7 0.8 Volts (sat.) γ Bulk Threshold Parameter λ Channel Length Modulation Parameter φ = 2φF Surface potential at strong inversion These values are based on a 0.8 µm silicon-gate bulk CMOS n-well process. Allen and Holberg - CMOS Analog Circuit Design Page III.1-15 WEAK INVERSION MODEL (Simple) iD (nA) Weak inversion region 1000.0 iD Strong inversion region 100.0 10.0 1.0 0 VT VON vGS 0 VT VON vGS This model is appropriate for hand calculations but it does not accommodate a smooth transition into the strong-inversion region. qvGS W iD ≅ L IDO exp nkT The transition point where this relationship is valid occurs at approximately kT vgs < V T + n q Weak-Moderate-Strong Inversion Approximation Moderate inversion region iD (nA) Weak inversion region 1000.0 100.0 Strong inversion region 10.0 1.0 0 vGS Allen and Holberg - CMOS Analog Circuit Design Page III.2-1 INTRINSIC CAPACITORS OF THE MOSFET Types of MOS Capacitors 1. Depletion capacitance (CBD and CBS) 2. Gate capacitances (CGS, CGD, and CGB) SiO2 Gate Source C1 Drain C2 C3 C4 CBD CBS Bulk Figure 3.2-4 Large-signal, charge-storage capacitors of the MOS device. Allen and Holberg - CMOS Analog Circuit Design Page III.2-2 Depletion Capacitors Bulk-drain pn junction CBD Capacitance approximation for strong forward bias CBD0xArea (FC).φ B Reverse Bias CBD = Forward φ B Bias VBD CBD0 A BD CBS0 ABS and CBS = vBD MJ vBS MJ 1 − 1 − φ B φ B where, A BD (ABS) = area of the bulk-drain (bulk-source) φΒ = bulk junction potential (barrier potential) MJ = bulk junction grading coefficient ( 0.33 ≤ MJ ≤ 0.5) For strong forward bias, approximate the behavior by the tangent to the above CBD or CBS curve at vBD or vBS equal to (FC)·φ B. CBD = CBD0A BD vBD 1 − (1+MJ)FC + FC , vBD > ( FC)·φ B (1+ FC)1+MJ φB CBD = CBS0ABS vBS 1 − (1+MJ)FC + FC , vBS > (FC)·φ B (1+ FC)1+MJ φB and Allen and Holberg - CMOS Analog Circuit Design Page III.2-3 Bottom & Sidewall Approximations Polysilicon gate H G C D Source Drain F E A B SiO2 Bulk Drain bottom = ABCD Drain sidewall = ABFE + BCGF + DCGH + ADHE CBX = (CJ )(AX) (CJSW)(PX) + , vBX ≤ (FC)(PB) vBX MJ vBX MJSW 1 − 1 − PB PB and CBX = vBX (CJ )(AX) 1 − (1 + MJ)FC + MJ PB (1 − FC)1+MJ + v (CJSW)(PX) 1 − (1 + MJSW )FC + BX (MJSW) , PB (1 − FC)1+MJSW vBX ≥ (FC)(PB) where AX = area of the source (X = S) or drain (X = D) PX = perimeter of the source (X = S) or drain (X = D) CJSW = zero-bias, bulk-source/drain sidewall capacitance MJSW = bulk-source/drain sidewall grading coefficient Allen and Holberg - CMOS Analog Circuit Design Page III.2-4 Overlap Capacitance Mask L Actual L (Leff) Oxide encroachment Mask W LD Actual W (Weff) Gate Source-gate overlap capacitance CGS (C1) Drain-gate overlap capacitance CGD (C3) Gate FOX Source Drain FOX Bulk Figure 3.2-5 Overlap capacitances of an MOS transistor. (a) Top view showing the overlap between the source or drain and the gate. (b) Side view. C1 = C3 ≅ (LD)(Weff )Cox = (CGXO)Weff Allen and Holberg - CMOS Analog Circuit Design Page III.2-5 Gate to Bulk Overlap Capacitance Overlap FOX C5 Overlap Gate C5 Source/Drain FOX Bulk Figure 3.2-6 Gate-bulk overlap capacitances. On a per-transistor basis, this is generally quite small Channel Capacitance C2 = Weff (L − 2 LD)Cox = Weff (Leff )Cox Drain and source portions depend upon operating condition of transistor. Allen and Holberg - CMOS Analog Circuit Design Page III.2-6 MOSFET Gate Capacitance Summary: Capacitance C2 + 2C5 CGS _ C1 + 2 C2 3 CGS, CGD _ C1 + 1 C2 2 CGS, CGD C1, C3 vDS = constant vBS = 0 CGD CGB 2C5 0 Off Saturation VT vDS +VT NonSaturation vGS Figure 3.2-7 Voltage dependence of CGS, CGD, and CGB as a function of VGS with VDS constang and VBS = 0. iD v DS = v GS - VT Non-Sat Region Saturation Region Cutoff Region 0 0 0.5 1.0 vDS = constant 1.5 2.0 2.5 Allen and Holberg - CMOS Analog Circuit Design CGS, CGD, and CGB Off CGB = C2 + 2 C5 = Cox(Weff )(Leff ) + CGBO(Leff ) CGS = C1 ≅ Cox(LD)(Weff ) = CGSO(Weff ) CGD = C3 ≅ Cox(LD)(Weff ) = CGD O(Weff ) Saturation CGB = 2 C5 = CGBO (Leff ) CGS = C1 + (2/3)C2 = Cox(LD + 0.67Leff )(Weff ) = CGSO(Weff ) + 0.67Cox(Weff )(Leff ) CGD = C3 ≅ Cox(LD)(Weff ) = CGD O(Weff ) Nonsaturated CGB = 2 C5 = CGBO (Leff ) CGS = C1 + 0.5C2 = Cox(LD + 0.5Leff )(Weff ) = (CGSO + 0.5CoxLeff )Weff CGD = C3 + 0.5C2 = Cox(LD + 0.5Leff )(Weff ) = (CGDO + 0.5CoxLeff )Weff Page III.2-7 Allen and Holberg - CMOS Analog Circuit Design Page III.3-1 Small-Signal Model for the MOS Transistor D rD Cbd inrD Cgd G gbd gds gmvgs B inD Cgs gmbsvbs gbs inrS Cgb Cbs rS S Figure 3.3-1 Small-signal model of the MOS transistor. gbd = ∂IBD ∂VBD (at the quiescent point) ≅ 0 and gbs = ∂IBS ∂VBS (at the quiescent point) ≅ 0 The channel conductances, gm, gmbs, and gds are defined as gm = ∂ ID ∂VGS gmbs = (at the quiescent point) ∂ ID ∂VBS (at the quiescent point) and gds = ∂ ID ∂VDS (at the quiescent point) Allen and Holberg - CMOS Analog Circuit Design Page III.3-2 Saturation Region gm = gmbs = Noting that (2K'W/L)| ID|(1 + λ VDS) ≅ (2K'W/L)|ID| −∂ ID ∂ I D ∂ VT = − ∂VSB ∂VT ∂VSB ∂ID −∂ ID = , we get ∂VT ∂VGS gmbs = gm gds = go = γ = η gm 2(2|φF| + VSB)1/2 ID λ 1 + λ VDS ≅ ID λ Relationships of the Small Signal Model Parameters upon the DC Values of Voltage and Current in the Saturation Region. Small Signal DC Current DC Current and DC Voltage Model Parameters Voltage 2K' W gm ≅ (2K' IDW/L)1/2 _ ≅ (V -V ) gmbs gds L GS T γ (2IDβ)1/2 2(2|φF | + VSB) 1/2 ≅ λ ID γ ( β (VGS −VT) ) 2(2|φF | + VSB)1/2 Allen and Holberg - CMOS Analog Circuit Design Page III.3-3 Nonsaturation region gm = ∂ Id = β VDS ∂VGS gmbs = ∂ ID βγ VDS = ∂VBS 2(2|φF | + VSB)1/2 and gds = β (VGS − VT − VDS) Relationships of the Small-Signal Model Parameters upon the DC Values of Voltage and Current in the Nonsaturation Region. Small Signal DC Voltage and/or Current Model Parameters Dependence = β VDS gm β γ VDS gmbs 2(2|φF | + VSB)1/2 = β (VGS − VT gds Noise 2 4kT i nrD = ∆f rD (A2) 2 4kT i nrS = ∆f rS (A2) and 8kT gm(1+η) (KF )ID 2 i nD = + ∆f (A2) 3 f Cox L2 − VDS) Allen and Holberg - CMOS Analog Circuit Design Page III.4-1 SPICE Level 3 Model The large-signal model of the MOS device previously discussed neglects many important second-order effects. Most of these second-order effects are due to narrow or short channel dimensions (less than about 3µm). We shall also consider the effects of temperature upon the parameters of the MOS large signal model. We first consider second-order effects due to small geometries. When vGS is greater than VT, the drain current for a small device can be given as Drain Current 1 + fb iDS = BETA vGS − VT − 2 vDE ⋅ vDE (1) Weff Weff = µeffCOX BETA = KP L Leff eff (2) Leff = L − 2(LD) (3) Weff = W − 2(WD) (4) vDE = min(vDS , vDS (sat)) (5) fb = fn + GAMMA ⋅ fs 4(PHI + vSB)1/2 (6) Note that PHI is the SPICE model term for the quantity 2φf . Also be aware that PHI is always positive in SPICE regardless of the transistor type (p- or n-channel). fn = DELTA πεsi Weff 2 ⋅ COX (7) 2 1/2 xj LD + wc wp − LD fs = 1 − 1− xj xj Leff xj + wp (8) wp = xd (PHI + vSB )1/2 (9) 2⋅εsi 1/2 xd = q ⋅ NSUB (10) Allen and Holberg - CMOS Analog Circuit Design 2 wp − k wp wc = xj k1 + k2 3 xj xj Page III.4-2 (11) k1 = 0.0631353 , k2 = 0.08013292 , k3 = 0.01110777 Threshold Voltage ETA⋅8.15-22 v + GAMMA ⋅ f ( PHI + v )1/2 + f ( PHI + v ) VT = Vbi − s SB n SB C L 3 DS ox eff (12) vbi = vfb + PHI (13) vbi = VTO − GAMMA ⋅ PHI (14) or Saturation Voltage vgs − VT vsat = (15) 1 + fb 1/2 2 2 vDS(sat) = vsat + vC − vsat + vC vC = VMAX ⋅ Leff µs (16) (17) If VMAX is not given, then vDS(sat) = vsat Effective Mobility µs = U0 when VMAX = 0 1 + THETA (vGS − VT) µeff = µs when VMAX > 0; otherwise µeff = µs vDE 1+ vC Channel-Length Modulation When VMAX = 0 (18) (19) Allen and Holberg - CMOS Analog Circuit Design Page III.4-3 1/2 ∆L = xd KAPPA (vDS − vDS(sat)) (20) when VMAX > 0 ∆L = − ep ⋅ xd 2 2 1/2 ep ⋅ xd 2 2 + 2 + KAPPA ⋅ xd 2 ⋅ (vDS − vDS(sat)) (21) where ep = iDS = vC (vC + vDS(sat)) Leff vDS (sat) iDS 1 − ∆L (22) (21) Weak Inversion Model (Level 3) In the SPICE Level 3 model, the transition point from the region of strong inversion to the weak inversion characteristic of the MOS device is designated as von and is greater than VT. von is given by von = VT + fast (1) q ⋅ NFS GAMMA ⋅ fs (PHI + vSB)1/2 + fn (PHI + vSB) kT 1 + + fast = COX 2(PHI + vSB) q (2) where N F S is a parameter used in the evaluation of v on and can be extracted from measurements. The drain current in the weak inversion region, vGS less than von , is given as vGS - von iDS = iDS (von , vDE , vSB) e fast (3) where iDS is given as (from Eq. (1), Sec. 3.4 with vGS replaced with von) 1 + fb v ⋅v iDS = BETAvon − VT − 2 DE DE (4) Allen and Holberg - CMOS Analog Circuit Design Page III.4-4 Typical Model Parameters Suitable for SPICE Simulations Using Level-3 Model (Extended Model). These Values Are Based upon a 0.8µm Si-Gate Bulk CMOS nWell Process Parameter Parameter Typical Parameter Value Symbol Description N-Channel P-Channel Units VTO Threshold V 0.7 ± 0.15 − 0.7 ± 0.15 UO mobility 660 210 cm2/V-s DELTA Narrow-width threshold 2.4 1.25 adjust factor ETA Static-feedback threshold 0.1 0.1 adjust factor KAPPA Saturation field factor in 0.15 2.5 1/V channel-length modulation THETA Mobility degradation factor 0.1 0.1 1/V NSUB Substrate doping cm-3 3× 1016 6× 1016 TOX Oxide thickness 140 140 Å XJ Mettallurgical junction 0.2 0.2 µm depth WD Delta width µm LD Lateral diffusion 0.016 0.015 µm NFS Parameter for weak 11 11 cm-2 7× 10 6× 10 inversion modeling CGSO F/m 220 × 10 −12 220 × 10 −12 CGDO F/m 220 × 10 −12 220 × 10 −12 CGBO F/m 700 × 10 −12 700 × 10 −12 CJ F/m2 770 × 10 −6 560 × 10 −6 CJSW F/m 380 × 10 −12 350 × 10 −12 MJ 0.5 0.5 MJSW 0.38 0.35 NFS Parameter for weak cm-2 7× 1011 6× 1011 inversion modeling Allen and Holberg - CMOS Analog Circuit Design Page III.4-5 Temperature Dependence The temperature-dependent variables in the models developed so far include the: Fermi potential, PHI, EG, bulk junction potential of the source-bulk and drain-bulk junctions, PB, the reverse currents of the pn junctions, IS, and the dependence of mobility upon temperature. The temperature dependence of most of these variables is found in the equations given previously or from well-known expressions. The dependence of mobility upon temperature is given as T BEX UO(T) = UO(T0) T0 where BEX is the temperature exponent for mobility and is typically -1.5. vtherm(T) = KT q T2 EG(T) = 1.16 − 7.02 ⋅ 10−4 ⋅ T + 1108.0 EG(T0) T T EG(T) − PHI(T) = PHI(T0) ⋅ − vtherm(T) 3 ⋅ ln + T0 T0 vtherm(T0) vtherm(T) vbi (T) = vbi (T0) + PHI(T) − PHI(T0) EG(T0) − EG(T) + 2 2 VT0(T) = vbi (T) + GAMMA PHI(T) NSUB PHI(T)= 2 ⋅ vtherm ln ni ( T ) ni(T) = 1.45 ⋅ 3/2 1016 T ⋅ T0 T 1 ⋅ exp EG ⋅ − 1 ⋅ T0 2 ⋅ vtherm(T ) 0 For drain and source junction diodes, the following relationships apply. EG(T0) T T EG(T) PB(T) = PB ⋅ − vtherm(T) 3 ⋅ ln + − T0 T0 vtherm(T0) vtherm(T) IS(T) = IS(T0) EG(T0) EG(T) T ⋅ exp − + 3 ⋅ ln vtherm(T0) vtherm(T) T0 N where N is diode emission coefficient. The nominal temperature, T0, is 300 K. Allen and Holberg - CMOS Analog Circuit Design Page III.3-1 SPICE Simulation of MOS Circuits Minimum required terms for a transistor instance follows: M1 3 6 7 0 NCH W=100U L=1U “M,” tells SPICE that the instance is an MOS transistor (just like “R” tells SPICE that an instance is a resistor). The “1” makes this instance unique (different from M2, M99, etc.) The four numbers following”M1” specify the nets (or nodes) to which the drain, gate, source, and substrate (bulk) are connected. These nets have a specific order as indicated below: M<number> <DRAIN> <GATE> <SOURCE> <BULK> ... Following the net numbers, is the model name governing the character of the particular instance. In the example given above, the model name is “NCH.” There must be a model description of “NCH.” The transistor width and length are specified for the instance by the “W=100U” and “L=1U” expressions. The default units for width and length are meters so the “U” following the number 100 is a multiplier of 10-6. [Recall that the following multipliers can be used in SPICE: M, U, N, P, F, for 10-3, 10-6, 10-9, 10-12 , 10 -15 , respectively.] Additional information can be specified for each instance. Some of these are Drain area and periphery (AD and PD) ← calc depl cap and leakage Source area and periphery (AS and PS) ← calc depl cap and leakage Drain and source resistance in squares (NRD and NRS) Multiplier designating how many devices are in parallel (M) Initial conditions (for initial transient analysis) The number of squares of resistance in the drain and source (NRD and NRS) are used to calculate the drain and source resistance for the transistor. Allen and Holberg - CMOS Analog Circuit Design Page III.3-2 Geometric Multiplier: M To apply the “unit-matching” principle, use the geometric multiplier feature rather than scale W/L. This: M1 3 2 1 0 NCH W=20U L=1U is not the same as this: M1 3 2 1 0 NCH W=10U L=1U M=2 The following dual instantiation is equivalent to using a multiplier M1A 3 2 1 0 NCH W=10U L=1U M1B 3 2 1 0 NCH W=10U L=1U (a) (b) (a)M1 3 2 1 0 NCH W=20U L=1U. (b) M1 3 2 1 0 NCH W=10U L=1U M=1. . Allen and Holberg - CMOS Analog Circuit Design Page III.3-3 MODEL Description A SPICE simulation file for an MOS circuit is incomplete without a description of the model to be used to characterize the MOS transistors used in the circuit. A model is described by placing a line in the simulation file using the following format. .MODEL <MODEL NAME> <MODEL TYPE> <MODEL PARAMETERS> MODEL NAME e.g., “NCH” MODEL TYPE either “PMOS” or “NMOS.” MODEL PARAMETERS : LEVEL=1 VTO=1 KP=50U GAMMA=0.5 LAMBDA=0.01 SPICE can calculate what you do not specify You must specify the following • surface state density, NSS, in cm-2 • oxide thickness, TOX, in meters • surface mobility, UO, in cm2/V-s, • substrate doping, NSUB, in cm-3 The equations used to calculate the electrical parameters are VTO = φMS − KP = UO (2q ⋅ εsi ⋅ NSUB ⋅ PHI)1/2 q(NSS) + + PHI (εox/TOX) (εox/TOX) εox TOX GAMMA = (2q ⋅ εsi ⋅ NSUB)1/2 (εox/TOX) and 2kT NSUB PHI = 2φF = q ln n i LAMBDA is not calculated from the process parameters for the LEVEL 1 model. Allen and Holberg - CMOS Analog Circuit Design Page III.3-4 Other parameters: IS: Reverse current of the drain-bulk or source-bulk junctions in Amps JS: Reverse-current density in A/m2 JS requires the specification of AS and AD on the model line. If IS is specified, it overrides JS. The default value of IS is usually 10-14 A. RD: Drain ohmic resistance in ohms RS: Source ohmic resistance in ohms RSH: Sheet resistance in ohms/square. RSH is overridden if RD or RS are entered. To use RSH, the values of NRD and NRS must be entered on the model line. The drain-bulk and source-bulk depletion capacitors CJ: Bulk bottom plate junction capacitance MJ: Bottom plate junction grading coefficient CJSW: Bulk sidewall junction capacitance MJSW: Sidewall junction grading coefficient If CJ is entered as a model parameter it overrides the calculation of CJ using NSUB, otherwise, CJ is calculated using NSUB. If CBD and CBS are entered, these values override CJ and NSUB calculations. In order for CJ to result in an actual circuit capacitance, the transistor instance must include AD and AS. In order for CJSW to result in an actual circuit capacitance, the transistor instance must include PD and PS. CGSO: CGDO: Gate-Source overlap capacitance (at zero bias) Gate-Drain overlap capacitance (at zero bias) AF: KF: Flicker noise exponent Flicker noise coefficient TPG: Indicates type of gate material relative to the substrate TPG=1 > gate material is opposite of the substrate TPG=-1 > gate material is the same as the substrate TPG=0 > gate material is aluminum XQC: Channel charge flag and fraction of channel charge attributed to the drain Allen and Holberg - CMOS Analog Circuit Design Page IV.0-1 IV. CMOS PROCESS CHARACTERIZATION Contents IV.1 IV.2 IV.3 IV.4 IV.5 Measurement of basic MOS level 1 parameters Characterization of the extended MOS model Characterization other active components Characterization of resistance Characterization of capacitance Organization Chapter 10 D/A and A/D Converters Chapter 11 Analog Systems SYSTEMS Chapter 7 CMOS Comparators Chapter 8 Simple CMOS Opamps Chapter 9 High Performance Opamps COMPLEX CIRCUITS Chapter 5 CMOS Subcircuits Chapter 6 CMOS Amplifiers SIMPLE Chapter 2 CMOS Technology Chapter 3 CMOS Device Modeling Chapter 4 Device Characterization DEVICES 1 Allen and Holberg - CMOS Analog Circuit Design I. Page IV.1-1 Characterization of the Simple Transistor Model Determine V T0(V SB = 0), K', γ, and λ . Terminology: K'S for the saturation region K'L for the nonsaturation region W eff (v iD = K ' S - V T )2 (1 + λ v DS ) 2L eff GS 2 v DS W eff ( v G S - V T ) v D S iD = K ' L 2 L eff VT = VT0 + γ 2|φ F | + vS B - 2|φ F | (1) (2) (3) Assume that vDS is chosen such that the λ vDS << 1 v SB =0 -> V T = V T 0 . Therefore, Eq. (1) simplifies to W eff (v iD = K’ S - V T 0 )2 2Leff GS (4) This equation can be manipulated algebraically to obtain the following 1/2 K' S W eff 1/2 1/2 K' S W eff iD = 2 L vGS - 2L VT0 eff eff which has the form y = mx + b 1/2 (5) (6) y = iD (7) x = v GS (8) 1 Allen and Holberg - CMOS Analog Circuit Design K' S W eff 1/2 m= 2 L eff Page IV.1-2 (9) and K' S W eff 1/2 b = − VT0 2 L eff 1/2 Plot i D (10) versus vGS and measure slope. to get K'S 1/2 When iD = 0 the x intercept (b') is V T 0 . 2 Allen and Holberg - CMOS Analog Circuit Design Page IV.1-3 Mobility degradation region v DS > VDSAT ( iD ) 1/2 Weak inversion region b ′ = VT 0 K S Weff ′ m= 2 L eff 1/2 v GS (a) v DS = 0 . 1 V iD K L Weff ′ m= L eff vDS vGS (b) Figure B.1-1 (a) iD1/2 versus vGS plot used to determine VT0 and K'S. (b) iD versus vGS plot to determine K'L. Extract the parameter K'L for the nonsaturation region: v D S W eff W eff v DS v GS - K ' L v DS V T + iD = K ' L 2 L eff L eff (11) Plot iD versus vGS as shown in Fig. B.1-1(b), the slope is seen to be 3 Allen and Holberg - CMOS Analog Circuit Design Page IV.1-4 ∆ iD W eff v m = ∆v = K'L L eff DS GS Knowing the slope, the term K'L is easily determined to be L eff W eff K' L = m 1 vDS (12) (13) W eff, Leff, and vDS must be known. The approximate value µo can be extracted from the value of K'L At this point, γ is unknown. Write Eq. (3) in the linear form where y = VT (14) 2 | φ F | + v SB − (15) x= 2|φ F | m=γ (16) b = VT0 (17) 2|φF| normally in the range of 0.6 to 0.7 volts. Determine VT at various values of vSB Plot VT versus x and measure the slope to extract γ Slope m, measured from the best fit line, is the parameter γ. 4 Allen and Holberg - CMOS Analog Circuit Design (i D ) Page IV.1-5 1/2 VT 0 VT 1 VT 2 VT 3 v GS Figure B.1-2 iD1/2 versus vGS plot at different vSB values to determine γ. VSB = 3 V VSB = 2 V VT VSB = 1 V m=γ VSB = 0 V ( vSB + 2 φ F ) 0.5 − ( 2 φF ) 0.5 Figure B.1-3 Plot of VT versus f(vSB) to determine γ. We still need to find λ, ∆L, and ∆W . λ should be determined for all device lengths that might be used. Rewrite Eq. (1) is as iD = i' D λ vDS + i' D (18) 5 Allen and Holberg - CMOS Analog Circuit Design which is in the familiar linear form where y = iD (Eq. (1)) Page IV.1-6 (19) x = v DS (20) m = λ i'D (21) b = i'D (Eq. (4) with λ = 0) (22) Plot iD versus v DS , and measure the slope of the data in the saturation region, and divide that value by the y-intercept to getλ. Saturation region Nonsaturation region iD i'D m = λ i'D v DS Figure B.1-4 Plot of iD versus vDS to determine λ. Calculating ∆L and ∆W. Consider two transistors, with the same widths but different lengths, operating in the nonsaturation region with the same vDS. The widths of the transistors are assumed to be very large so that W ≅ Weff. The large-signal model is given as 2 v K ' L W eff ( v DS iD = L - V T 0 ) v D S - 2 eff G S (23) 6 Allen and Holberg - CMOS Analog Circuit Design Page IV.1-7 and K' L W eff ∂ ID VD S = gm = ∂ V GS L eff The aspect ratios (W /L) for the two transistors are W1 L1 + ∆L (24) (25) and W2 L2 + ∆L (26) Implicit in Eqs. (25) and (26) is that ∆L is assumed to be the same for both transistors. Combining Eq. (24) with Eqs. (25) and (26) gives K'LW (27) gm 1 = L + ∆ L v DS 1 and K'LW gm 2 = L + ∆ L v DS 2 (28) where W 1 = W 2 = W (and are assumed to equal the effective width). With further algebraic manipulation of Eqs. (27) and (28), one can show that, L2 + ∆L gm 1 = (29) gm1 - gm2 L2 - L1 which further yields (L 2 - L 1) gm 1 L 2 + ∆ L = L eff = g m1 - gm2 (30) L2 and L1 known gm1 and gm2 can be measured Similarly for W eff : (W 1 - W 2)g m 2 W 2 + ∆ W = W eff = g m1 - gm2 (31) Equation (31) is valid when two transistors have the same length but different widths. 7 Allen and Holberg - CMOS Analog Circuit Design Page IV.1-8 One must be careful in determining ∆L (or ∆W ) to make the lengths (or widths) sufficiently different in order to avoid the numerical error due to subtracting large numbers, and small enough that the transistor model chosen is still valid for both transistors. 8 Allen and Holberg - CMOS Analog Circuit Design Page IV.3-1 II. Transistor Characterization for the Extended Model Equations (1) and (2) represent a simplified version of the extended model for a relatively wide MOS transistor operating in the nonsaturation, stronginversion region with VSB = 0. µsCoxW iD = L v2 (v DS - V T ) v D S - 2 + γvDS GS 2|φ F | 2γ − 3 [ ( v DS + 2 | φ F |) 1.5 - ( 2| φ F |)] 1.5 (1) where W and L are effective electrical equivalents (dropping the subscript, “eff”, for convenience). (UCRIT)εsi UEXP Cox [ v GS - V T - ( UTRA) v DS ] µs = µo (2) Eq. (2) holds when the denominator term in the brackets is less than unity. Otherwise, µo = µs. To develop a procedure for extracting µo, consider the case where mobility degradation effects are not being experienced, i.e., µs = µo, Eq. (1) can be rewritten in general as (3) iD = µ o f(C ox , W , L , v GS , V T , v DS , γ , 2|φ F |) This equation is a linear function of vGS and is in the familiar form of y = mx + b (4) where b = 0. Plot iD versus the function, f(Cox, W , L , v GS , V T , v DS , γ , 2 |φ F |) and measure the slope = µo. • • • The data are limited to the nonsaturation region (small vDS ). The transistor must be in the strong-inversion region (vGS > VT). The transistor must operate below the critical-mobility point. Keep vGS as low as possible without encroaching on the weak-inversion region of operation. 1 Allen and Holberg - CMOS Analog Circuit Design Page IV.3-2 Region of variable mobility iD Region of constant mobility Weak-inversion region v GS Figure B.2-1 Plot of iD versus vGS in the nonsaturation region. Once µo is determined, there is ample information to determine UCRIT and UEXP. Consider Eqs. (1) and (2) rewritten and combined as follows. iD = µo[(UCRIT)f2]UEXPf1 (5) where 2 v C ox W DS f1 = L ( v G S - V T ) v D S - 2 + γ vDS 2| φ F | 2γ − 3 [ ( v DS + 2 | φ F |) 1.5 - ( 2| φ F |)] 1.5 (1) and 2 Allen and Holberg - CMOS Analog Circuit Design f2 = ε si [ v GS - V T - ( UTRA) v DS ] C o x Page IV.3-3 (7) The units of f 1 and f 2 are FV2/cm2 and cm/V respectively. Notice that f 2 includes the parameter UTRA, which is an unknown. UTRA is disabled in most SPICE models. Equation (5) can be manipulated algebraically to yield iD = log( µo) + UEXP[log(UCRIT)] + UEXP[log(f2)] (8) f1 log This is in the familiar form of Eq. (4) with x = log(f2) (9) iD y = log f 1 (10) m = UEXP (11) b = log( µo) + UEXP[log(UCRIT)] (12) By plotting Eq. (8) and measuring the slope, UEXP can be determined. The y-intercept can be extracted from the plot and UCRIT can be determined by back calculation given UEXP, µo, and the intercept, b. 3 Allen and Holberg - CMOS Analog Circuit Design Page IV.4-1 III. Characterization of Substrate Bipolar Parameters of interest are: β dc , and JS. For v BE >> k T/q, k T iC v BE = q ln JSA E (1) and iE βdc = i − 1 (2) B AE is the cross-sectional area of the emitter-base junction of the BJT. iE = iB (β dc + 1) (3) Plot iB as a function of iE and measure the slope to determine β dc. Once β dc is known, then Eq. (1) can be rearranged and modified as follows. k T iE β d c kT kT kT − v BE = q ln ln(JSAE) = q ln(α dc iE) − q q 1 + β d c ln( JSAE) Plotting ln[iEβ dc/(1 + β dc)] versus vBE results in a graph where kT m = slope = q (5) and k T ln(JSA E ) q b = y-intercept = − (6) Since the emitter area is known, JS can be determined directly. 1 Allen and Holberg - CMOS Analog Circuit Design IV. Page IV.5-1 Characterization of Resistive Components • Resistors • Contact resistance Characterize the resistor geometry exactly as it will be implemented in a design. Because • sheet resistance is not constant across the width of a resistor • the effects of bends result in inaccuracies • termination effects are not accurately predictable Figure B.5-1 illustrates a structure that can be used to determine sheet resistance, and geometry width variation (bias). Force a current into node A with node F grounded while measuring the voltage drops across BC (Vn) and DE (Vw), the resistors Rn and Rw can be determined as follows Vn Rn = (1) I Rw = Vw I (2) The sheet resistance can be determined from these to be W n - B ias Ln (3) W w - B ias Lw (3) RS = Rn RS = Rw where Rn = resistance of narrow resistor (Ω ) Rw = resistance of wide resistor (Ω) R S = sheet resistance of material (polysilicon, diffusion etc. Ω/square) Ln = drawn length of narrow resistor 1 Allen and Holberg - CMOS Analog Circuit Design Page IV.5-2 Lw = drawn length of wide resistor W n = drawn width of narrow resistor W w = drawn width of wide resistor Bias = difference between drawn width and actual device width Rw Rn A Wn Ln B F Ww Lw C D E Figure B.5-1 Sheet resistance and bias monitor. Solving equations (3) and (4) yields W n - k Ww Bias = 1 - k (5) RwLn k=R L nw (6) where and W n - B ias W w - B ias = Rw Ln Lw RS = Rn (7) 2 Allen and Holberg - CMOS Analog Circuit Design Page IV.5-3 Determining sheet resistance and contact resistance 10 squares RA=220 Ω 20 squares RB=420 Ω Figure B.5-2 Two resistors used to determine RS and RC. R A = R 1 + 2R c ; R1 = N 1RS (8) R B = R 2 + 2R c ; R2 = N 2RS N1 is the number of squares for R1 RS is the sheet resistivity in Ω/square Rc is the contact resistance. RB - RA RS = N - N 2 1 (9) and (10) and 2Rc = RA − N 1RS = RB − N 2RS (11) 3 Allen and Holberg - CMOS Analog Circuit Design Page IV.5-4 Voltage coefficient of lightly-doped resistors R= V1 − V2 IR VBIAS = V1 + V2 2 IR V1 V2 VSS Figure B.5-3 N-well resistor illustrating back-bias dependence. 27.0 Resistance (kΩ) 26.5 26.0 25.5 25.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Back bias (volts) Figure B.5-4 N-well resistance as a function of back-bias voltage 4 Allen and Holberg - CMOS Analog Circuit Design Page IV.5-5 Contact Resistance Pad 1 Metal pads Diffusion or polysilicon Pad 3 Pad 4 Metal pads Pad 2 Pad 1 RC R RC Pad 4 R RC Pad 3 RM RM Pad 2 5 Allen and Holberg - CMOS Analog Circuit Design Page IV.5-1 V. Characterization of Capacitance MOS capacitors CGS, CGD, and CGB Depletion capacitors CDB and CSB Interconnect capacitances Cpoly-field, Cmetal-field, and Cmetal-poly (and perhaps multi-metal capacitors SPICE capacitor models C GS0, C GD 0, and C GB0 (at V GS = V GB = 0). Normally SPICE calculates CDB and CSB using the areas of the drain and source and the junction (depletion) capacitance, CJ (zero-bias value), that it calculates internally from other model parameters. Two of these model parameters, MJ and MJSW , are used to calculate the depletion capacitance as a function of voltage across the capacitor. 1 Allen and Holberg - CMOS Analog Circuit Design Page IV.5-2 C GS 0 , C GD 0 , and C GB 0 CGS0 and CGD0, are modeled in SPICE as a function of the device width, while the capacitor CGB0 is per length of the device Measure the CGS of a very wide transistor and divide the result by the width in order to get CGS0 (per unit width). Source Drain Source Gate Figure B.6-1 Structure for determining CGS and CGD. Cmeas = W(n)(CGS0 + CGD 0) (1) where Cmeas = total measured capacitance W = total width of one of the transistors n = total number of transistors 2 Allen and Holberg - CMOS Analog Circuit Design Page IV.5-3 For very narrow transistors, the capacitance determined using the previous technique will not be very accurate because of fringe field and other edge effects at the edge of the transistor. In order to characterize CGS 0 and CGD0 for these narrow devices, a structure similar to that given in Fig. B.6-1 can be used, substituting different device sizes. Such a structure is given in Fig. B.6-3. The equations used to calculate the parasitic capacitances are the same as those given in Eq. (1). Metal drain interconnect Drain Source Metal source interconnect Drain Polysilicon gate Source Figure B.6-3 Structure for measuring CGS and CGD, including fringing effects, for transistors having small L. 3 Allen and Holberg - CMOS Analog Circuit Design Page IV.5-4 CGB0 Drain Gate overhang Gate Source FOX Diffusion source CGB FOX Cpoly-field Figure B.6-4 Illustration of gate-to-bulk and poly-field capacitance. This capacitance is approximated from the interconnect capacitance Cpoly-field (overhang capacitor is not a true parallel-plate capacitor) Cmeas (F/m2 ) (2) Cpoly-field = L W RR where Cmeas = Cmeas = measured value of the polysilicon strip LR = length of the centerline of the polysilicon strip WR = width of the polysilicon strip (usually chosen as device length) Having determined Cpoly-field, CGB0 can be approximated as CGB 0 ≅ 2 ( Cpoly-field)(doverhang) = 2C 5 (F/m) (3) where doverhang = overhang dimension (see Rule 3D, Table 2.6-1) 4 Allen and Holberg - CMOS Analog Circuit Design Page IV.5-5 C BD and C BS VJ CJ(VJ) = ACJ(0)1 + PB -MJ VJ + PCJSW(0)1 + PB -MJSW (4) where VJ = the reverse bias voltage across the junction CJ(VJ) = bottom junction capacitance at VJ CJSW(VJ) = junction capacitance of sidewall at VJ A = area of the (bottom) of the capacitor P = perimeter of the capacitor PB = bulk junction potential The constants CJ and MJ can be determined by measuring a large rectangular capacitor structure where the contribution from the sidewall capacitance is minimal. For such a structure, CJ(VJ) can be approximated as VJ -MJ (5) CJ(VJ) = ACJ(0)1 + PB This equation can be rewritten in a way that is convenient for linear regression. VJ 1 + log[CJ(VJ)] = (−MJ)log PB + log[ACJ(0)] (6) Plotting log[CJ(VJ)] versus log[1 + VJ/PB] and determine the slope, −MJ, and the Y intercept (where Y is the term on the left), Log[ACJ(0)]. Knowing the area of the capacitor, the calculation of the bottom junction capacitance is straightforward. 5 Allen and Holberg - CMOS Analog Circuit Design Page V.0-1 V. CMOS SUBCIRCUITS Contents V.1 V.2 V.3 V.4 V.5 V.6 MOS Switch MOS Diode MOS Current Source/Sinks Current Mirrors/Amplifiers Reference Circuits V.5-1 Power Supply Dependence V.5-2 Temperature Dependence Summary O rganization Chapter 10 D/A and A/D Converters Chapter 11 Analog Systems SYSTEMS Chapter 7 CMOS Comparators Chapter 8 Simple CMOS Opamps Chapter 9 High Performance Opamps COMPLEX CIRCUITS Chapter 5 CMOS Subcircuits Chapter 6 CMOS Amplifiers SIMPLE Chapter 2 CMOS Technology DEVICES Chapter 3 CMOS Device Modeling Chapter 4 Device Characterization Allen and Holberg - CMOS Analog Circuit Design Page V.0-2 WHAT IS A SUBCIRCUIT? A subcircuit is a circuit which consists of one or more transistors and generally perfoms only one function. A subcircuit is generally not used by itself but in conjunction with other subcircuits. Example Design hierarchy of analog circuits illustrated by an op amp. Operational Amplifier Complex Circuits Simple Circuits Biasing Circuits Current Source Current Mirror Input Differential Amplifier Current Sink Diff. Amp. Mirror Load Second Gain Stage Inverter Output Stage Current Source Current Sink Sink Load Follower Load Allen and Holberg - CMOS Analog Circuit Design Page V.1-1 V.1 - MOS SWITCH SWITCH PROPERTIES Ideal Switch RAB(on) = 0Ω A B RAB(off) = ∞ Nonideal Switch CAB IOFF ROFF VOFF RON + - A B CAC C + RA VControl - CBC RB Allen and Holberg - CMOS Analog Circuit Design Page V.1-2 MOS TRANSISTOR AS A SWITCH Symbol Bulk B A B (S/D) A (D/S) C (G) On Characteristics of A MOS Switch Assume operation in non-saturation region (vDS < vGS - V T). v D S K’W (v G S - V T ) iD = L 2 vDS ∂iD K’W ∂vDS = L v G S − V T − v D S Thus, ∂vDS 1 RON = ∂i = K’W D (vG S − V T − vD S ) L OFF Characteristics of A MOS Switch If vGS < VT, then iD = I OFF = 0 when vDS ≈ 0V. If vDS > 0, then 1 1 ≈∞ ROFF ≈ i λ = I DS OFFλ Allen and Holberg - CMOS Analog Circuit Design Page V.1-3 MOS SWITCH VOLTAGE RANGES Assume the MOS switch connects to circuits and the analog signal can vary from 0 to 5V. What are the voltages required at the terminals of the MOS switch to make it work properly? Bulk (0 to 5V) Circuit 1 (0 to 5V) (S/D) (D/S) Circuit 2 G • The bulk voltage must be less than or equal to zero to insure that the bulk-source and bulk-drain are reverse biased. • The gate voltage must be greater than 5 + VT in order to turn the switch on. Therefore, VBulk ≤ 0V V G ≥ 5 + VT (Remember that the larger the value of VSB , the larger VT) Allen and Holberg - CMOS Analog Circuit Design Page V.1-4 I-V CHARACTERISTICS OF THE MOS SWITCH SPICE ON Characteristics of the MOS Switch 100µA V1 =10V V1 V1=9V Id 60µA V1 =8V V1 =7V V2 -5 20µA Id -20µA V1=2V V1=3V V1=4V -60µA V1 =5V -100µA -1V V1 =6V -0.6V -0.2V 0.2V V2 SPICE Input File: MOS Switch On Characteristics M1 1 2 0 3 MNMOS W=3U L=3U .MODEL MNMOS NMOS VTO=0.75, KP=25U, +LAMBDA=0.01, GAMMA=0.8 PHI=0.6 V2 1 0 DC 0.0 V1 2 0 DC 0.0 V3 3 0 DC -5.0 .DC V2 -1 1 0.1 V1 2 10 1 .PRINT DC ID(M1) .PROBE .END 0.6V 1V Allen and Holberg - CMOS Analog Circuit Design Page V.1-5 MOS SWITCH ON RESISTANCE AS A FUNCTION OF VGS SPICE ON Resistance of the MOS Switch 100kΩ MOS Switch On Resistance W/L = 3µm/3µm 10kΩ W/L = 15µm/3µm W/L = 30µm/3µm 1kΩ W/L = 150µm/3µm 100Ω 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V Gate-Source Voltage 4.0V 4.5V 5.0V SPICE Input File: MOS Switch On Resistance as a f(W/L) M1 1 2 0 0 MNMOS W=3U L=3U M2 1 2 0 0 MNMOS W=15U L=3U M3 1 2 0 0 MNMOS W=30U L=3U M4 1 2 0 0 MNMOS W=150U L=3U .MODEL MNMOS NMOS VTO=0.75, KP=25U, LAMBDA=0.01, GAMMA=0.8 PHI=0.6 VDS 1 0 DC 0.001V VGS 2 0 DC 0.0 .DC VGS 1 5 0.1 .PRINT DC ID(M1) ID(M2) ID(M3) ID(M4) .PROBE .END Allen and Holberg - CMOS Analog Circuit Design Page V.1-6 INFLUENCE OF SWITCH IMPERFECTIONS ON PERFORMANCE Finite ON Resistance Non-zero charging and discharging rate. φ1 RON + VIN - VSS C1 + + vC1 C1 VIN - - + vC1 - Finite OFF Current φ1 φ1 C2 + vIN - VSS CHold + vOUT - + VSS vOUT - Allen and Holberg - CMOS Analog Circuit Design Page V.1-7 EXAMPLES 1. What is the on resistance of an enhancement MOS switch if VS = 0V, VG = 10V, W/L = 1, VTO = 1V, and K' = 25µA/V2? Assume that vDS ≈ 0V. Therefore, vDS L/W RON ≈ = K'(V -V -V ) iD GS T RON = 106 25(10-1) = 4444Ω VG 2. If V G=10V at t=0, what is the W/L value necessary to discharge C1 to with 5% of its intial charge at t=0.1µS? Assume K'=25µA/V2 and V TO = 1V. C2=10pF + 5V + - C1=20pF v(t) = 5exp(-t/RC) → 10-7 10-7 = 20 → RC = exp RC ln(20) 10 Therefore, R = 6 x 103Ω Thus, 10x103 L/W L/W = K'(V -V -V ) = 6 (2.5x10-5)(9) GST W Gives L = 2.67 - Allen and Holberg - CMOS Analog Circuit Design Page V.1-8 INFLUENCE OF PARASITIC CAPACITANCES MOSFET Model for Charge Feedthrough Analysis Distributed Model G CGDO CGSO D S CGC=Cox RCH Simplified Distributed Model G CGDO D Cox 2 Cox 2 CGSO S RCH CGSO = Voltage independent (1st-order), gate-source, overlap cap. CGDO = Voltage independent (1st order), drain-source overlap cap. CGC = Gate-to-channel capacitance (C ox) RCH = Distributed drain-to-source channel resistance Allen and Holberg - CMOS Analog Circuit Design Page V.1-9 Charge Injection Sensitivity to Gate Signal Rate Model: vG dvG dt + vIN CHold - Case 1 - Slow Fall Time: • Gate is inverted as vG goes negative . • Channel time constant small enough so that the charge on CHold is absorbed by vIN. • When gate voltage reaches vIN+VT, the device turns off and feedthru occurs via the overlap capacitance. Case 2 - Fast Fall Time: • Gate is inverted as vG goes negative. • Fall rate is faster than the channel time constant so that feedthru occurs via the channel capacitance onto CHold which is not absorbed by v IN. • Feedthru continues when vG reaches vIN+VT. • Total feedthru consists of that due to both the channel capacitance and the overlap capacitances. Other Considerations: • Source resistance effects the amount of charge shared between the drain and the source. • The maximum gate voltage before negative transition effects the amount of charge injected. Allen and Holberg - CMOS Analog Circuit Design Page V.1-10 Intuition about Fast and Slow Regimes To develop some intuition about the fast and slow cases, it is useful to model the gave voltage as a piecewise constant waveform (a quantized waveform) and consider the charge flow at each transition as illustrated below. In this figure, the range of voltage at CL illustrated represent the period while the transistor is on. In both cases, the quantized voltage step is the same, but the time between steps is different. The voltage accross CL is observed to be an exponential whose time constant is due to the channel resistance and channel capacitance and does not change from fast case to slow case. vCL ∆V vGATE Voltage Time (d) ∆V Voltage Time (e) Figure 4.1-10 (a) Illustration of slow ramp and (b) fast ramp using a quantized voltage ramp to illustrate the effects due to the time constant of the channel resistance and capacitance. Allen and Holberg - CMOS Analog Circuit Design Page V.1-11 Illustration of Parasitic Capacitances φ1 CGS + CGD VSS VIN CBS - CBD C1 + vC1 - CGS and CGD result in clock feedthrough CBS and CBD cause loading on the desired capacitances Clock Feedthrough Assume slow fall and rise times φ1 ∆φ1 Switch ON Switch OFF φ1 CGS + VIN - Clock signal couples through CGD on the rising part of signal when switch is off, but V charges C1 to the right value regardless. IN VSS CBS Clock signal couples through CGD on the falling part of the signal when the switch is off. CGD C1 + vC1 - CGD CGD CGD ∆vC1 = -C +C ∆φ 1 ≈ - C ∆φ 1 = - C (v in + VT) 1 GD 1 1 Allen and Holberg - CMOS Analog Circuit Design EXAMPLE regime) Switched Capacitor Page V.1-12 Integrator (slow clock edge φ1 Switch ON Switch OFF vIN+VT φ2 Switch ON Switch OFF VT T φ1 t t 1 2 t 3 t 4 φ2 M1 M2 + + VIN - assuming: C2 VSS C1 VSS vOUT - CGS1=CGS2=CGD1=CGD2 = CG Net feedthrough on C1 at t2: CG (VIN + VT) CG+C1 CG CG VC1 = VIN 1 − −V T C1+CG CG+C1 ∆V C1 = − At t3, additional charge has been added due to CGS overlap of M2 as φ2 goes positive. Note that M2 has not turned on yet. CG ∆V C1 (t2-t3) = C +C VT G 1 Allen and Holberg - CMOS Analog Circuit Design Page V.1-13 Giving at the end of t3 (before M2 turns on): CG VC1 = VIN 1−C +C 1 G + Once M2 turns on (at t3 ), all of the charge on C1 is transferred to C2. CG C1 C1 ∆VO = −VC1 = −V IN 1 − C1+CG C2 C2 + Between times at t3 and t4 additional charge is transferred to C1 from the channel capacitance of M2. ∆VO Cch (Vclk −V T) C2 (t3-t4)= − The final change in Vout is: CG C1 Cch ∆V O = −V IN 1− − (Vclk − V T) C2 C1+CG C2 C1 so the error due to charge C2 Ideally the output voltage change is −VIN feedthrough is: C1 CG Cch ∆ V O (error) = VIN − (Vclk − V T) C2 C1+CG C2 Allen and Holberg - CMOS Analog Circuit Design Page V.1-14 Rigorous Quantitative Analysis of Fast and Slow Regimes Consider the gate voltage traversing from VH to VL (e.g., 5.0 volts to 0.0 volts, respectively) described in the time domain as vG = V H − Ut (3) When operating in the slow regime defined by the relationship 2 β V HT 2CL >> U (4) where VHT is defined as V HT = V H − V S − V T (5) the error (the difference between the desired voltage V S and the actual voltage, VCL) due to charge injection can be described as Allen and Holberg - CMOS Analog Circuit Design W · C G D 0 V error = CL + C c h 2 Page V.1-15 π U CL W · C G D 0 + (V S + V T − V L ) 2β CL (6) In the fast swithing regime defined by the relationship 2 β V HT 2CL << U (7) the error voltage is given in Eq. (8) below as W· CGD0 + C ch 2 V error = V H T CL β V HT W·CGD0 − 6 U C + C (V S + V T − V L ) L L 3 (8) The following example illustrates the application of the charge-feedthrough model given by Eq’s. (3) through (8). Example 4.1-1 Calculation of charge feedthrough error Calculate the effect of charge feedthrough on the circuit shown in Fig. 4.1-9 where Vs = 1.0 volts, CL = 200 fF, W/L = 0.8µm/0.8µm, and VG is given for two cases illustrated below. Use model parameters from Tables 3.1-2 and 3.2-1. Neglect ∆L and ∆W effects. 5 Case 2 vG Case 1 0 0.2 ns 10 ns Time Case 1: The first step is to determine the value of U in the expression vG = VH - Ut For a transition from 5 volts to 0 volts in 0.2 ns, U = 25 × 109 In order to determine operating regime, the following relationship must be tested. Allen and Holberg - CMOS Analog Circuit Design Page V.1-16 2 2 β VHT β VHT 2CL >> U for slow or 2CL << U for fast Observin g that there is a backbias on the transistor switch effecting VT, VHT is VHT = VH - VS - VT = 5 - 1 - 0.887 = 3.113 giving 2 β VHT 110×10-6× 3.1132 = 2.66 × 109 << 25 × 109 thus fast regime. 2C L = 2 × 200f Applying Eq. (8) for the fast regime yields 1.58×10-15 176×10-18 + 3.32×10-3 176×10-18 2 Verror = (5 + 0.887 - 0) 3.113 + 200×10-15 30×10-3 200×10-15 Verror = 19.7 mV Case 2: The first step is to determine the value of U in the expression v G = VH - Ut For a transition from 5 volts to 0 volts in 10 ns, U = 5 × 108 thus indicating the slow regime according to the following test 2.66 × 109 >> 5 × 108 1.58×10-15 176×10-18 + 2 Verror = 200×10-15 Verror = 10.95 mV 314×10-6 176×10-18 + (5 + 0.887 - 0 ) 220×10-6 200×10-15 Allen and Holberg - CMOS Analog Circuit Design Page V.1-17 POSSIBLE SOLUTIONS TO CLOCK FEEDTHROUGH 1.) Dummy transistor (MD) φ φ W1 L1 WD = W1 LD 2L1 M1 MD VSS VSS Complete cancellation is difficult. Requires a complementary clock. 2.) Limit the clock swing when one terminal of the switch is at a defined potential. vG 0V C + + vin > 0 - vout VSS - vG 3VT 2VT VT t ON OFF ON Allen and Holberg - CMOS Analog Circuit Design Page V.1-18 CMOS SWITCHES "Transmission Gate" φ A VSS VDD φ Advantages 1.) Larger dynamic range. 2.) Lower ON resistance. Disadvantages 1.) Requires complementary clock. 2.) Requires more area. B Allen and Holberg - CMOS Analog Circuit Design Page V.1-19 DYNAMIC RANGE LIMITATIONS OF SWITCHES Must have sufficient vGS to give a sufficiently low on resistance Example: VDD 50µ 2µ A B VDD + VAB 1 µA 50µ 2µ - Switch On Resistance 3kΩ 2.5kΩ VDD = 4V 2kΩ VDD = 4.5V 1.5kΩ VDD = 5V 1kΩ 0.5kΩ 0kΩ 0V 1V 2V VAB 3V 4V 5V SPICE File: Simulation of the resistance of a CMOS transmission switch M1 1 3 2 0 MNMOS L=2U W=50U M2 1 0 2 3 MPMOS L=2U W=50U .MODEL MNMOS NMOS VTO=0.75, KP=25U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5 .MODEL MPMOS PMOS VTO=-0.75, KP=10U,LAMBDA=0.01, GAMMA=0.5, PHI=0.5 VDD 3 0 VAB 1 0 IA 2 0 DC 1U .DC VAB 0 5 0.02 VDD 4 5 0.5 .PRINT DC V(1,2) .END Allen and Holberg - CMOS Analog Circuit Design Page V.1-20 “Brooklyn Bridge” Effect If N-channel and P-channel devices are “resistively” scaled (i.e., sized to have the same conductance at equivalent terminal conditions) the resistance versus voltage (common mode) will appear as shown below. Nch on; Pch on Nch on Pch off Pch on Nch off 280 270 5v 260 R Id 250 5v 240 V 230 220 0.1 210 0 1 2 3 V 4 5 Allen and Holberg - CMOS Analog Circuit Design Page V.1-21 VOLTAGE DOUBLER USE TO PROVIDE GATE OVERDRIVE Example VDD φA M1 φA CPump M6 M4 M2 + φA M7 M8 VDBL φB CHold M3 φB φA φB M5 VSS φA φB Operation: 1. φA low, φB high - C Pump is charged to VDD-VSS. 2. φA high, φB low - CPump transfers negative charge to CHold VDBL ≈ -0.5V DD - V S S 3. Eventually, VDBL approaches the voltage of -VDD + VSS. If VDD = - VSS, then VDBL ≈ - 2VDD. - Allen and Holberg - CMOS Analog Circuit Design Page V.1-22 SUMMARY OF MOS SWITCHES • Symmetrical switching characteristics • High OFF resistance • Moderate ON resistance (OK for most applications) • Clock feedthrough is proportional to size of switch (W) and inversely proportional to switching capacitors. • Complementary switches help increase dynamic range. • As power supply reduces, switches become more difficult to fully turn on. • Switches contribute a kT/C noise which folds back into the baseband. Allen and Holberg - CMOS Analog Circuit Design Page V.2-1 V.2 - DIODES AND ACTIVE RESISTORS MOS ACTIVE RESISTORS Realizations + i + v i v - - When the drain is connected to the gate, the transistor is always saturated. vDS ≥ v GS - VT v D - vS ≥ v G - vS - VT ∴ vDG ≥ -V T where V T > 0 Large Signal I-V Characteristics i AC DC K 'W i = iD = ( ) [ vGS - VT ]2 2L β = 2 ( vGS - VT ) 2 , ignore λ or v v = vDS = vGS = VT + Small signal i G D + v S gm v gmbs vbs rds - S v If VBS = 0 , then ROUT = i If V BS ≠ 0? Note: 1 1 = g +g ≈g M DS M Generally, gm ≈ 10 gmbs ≈ 100 gds 2iD β Allen and Holberg - CMOS Analog Circuit Design Page V.2-2 VOLTAGE DIVISION USING ACTIVE RESISTORS Objective : Derive a voltage Vout from VSS and VDD VDD M2 Vout M1 VSS Equating iD1 to iD2 results in : vDS1 = β2 β1 v DS2 - V T 2 + VT1 where vGS1 = vDS1 and v GS2 = vDS2 Example : If VDD = -VSS = 5 volts, Vout = 1 volt, and ID1 = ID2 = 50 µamps, then use the model parameters of Table 3.1-2 to find W/L ratios. β iD1 = ( vGS - VT ) 2 2 β 1 = 4.0 µA/V2 β 2 = 11.1 µA/V2 K'n = 17 µA/V2 K'p = 8 µA/V2 1 then ( W/L )1 = 4.25 and ( W/L )2 = 1.34 Allen and Holberg - CMOS Analog Circuit Design Page V.2-3 EXTENDED DYNAMIC RANGE OF ACTIVE RESISTORS Concept: I VC + I1 M1 + vDS I I2 M2 - + VC - R Consider : Assume both devices are non-saturated 2 v DS I1 = β 1 (v DS + V C - V T )v DS 2 2 v DS I2 = β 2 (V C - V T )v DS - 2 2 2 v DS v DS I = I1 + I2 = β v D S 2 + ( V C - V T )v D S - 2 + ( V C - V T )v D S - 2 I = 2β(VC - VT)vDS 1 R = 2 β (V - V ) C T Allen and Holberg - CMOS Analog Circuit Design Page V.2-4 Implementation : VDD + V -C M3A S M2A M1 + VGS G- i M3B + VGS D S - M2 vDS + R VSS i G S M2B Allen and Holberg - CMOS Analog Circuit Design Page V.2-5 NMOS Parallel Transistor Realization : + i1 VC + G1 i D1 - + D2 i2 i G2 + M1 v VSS S1 M2 r ac v VC - S2 _ Voltage-Current Characteristic : 2mA Vc=7V 6V 5V I(VSENSE) 1mA 4V W=15u L=3u VBS=-5.0V 3V 0 -1mA -2mA -2 -1 0 VDS 1 NMOS parallel transistor realization M1 2 1 0 5 MNMOS W=15U L=3U M2 2 4 0 5 MNMOS W=15U L=3U .MODEL MNMOS NMOS VTO=0.75, KP=25U, LAMBDA=0.01, GAMMA=0.8 PHI=0.6 VC 1 2 E1 4 0 1 2 1.0 VSENSE 10 2 DC 0 VDS 10 0 VSS 5 0 DC -5 .DC VDS -2.0 2.0 .2 VC 3 7 1 .PRINT DC I(VSENSE) .PROBE .END 2 Allen and Holberg - CMOS Analog Circuit Design Page V.2-6 P-Channel Extended Range Active Resistor Circuit vAB iAB V DD M2B M2A + VC - M1A + VC M1B M3A +V C M3B - V SS Voltage Current Characteristics 100uA 4V 5V 60uA 3V 20uA Vc=2V i AB - 20uA - 60uA - 100uA -4 -3 -2 -1 0 1 VAB 2 3 4 P-Channel Extended Range Active Resistor M1A 3 4 5 10 MPMOS W=3U L=3U M1B 3 6 5 10 MPMOS W=3U L=3U M2A 10 3 4 4 MNMOS W=3U L=3U M2B 10 5 6 6 MNMOS W=3U L=3U M3A 4 7 0 0 MNMOS W=3U L=3U M3B 6 7 0 0 MNMOS W=3U L=3U VSENSE 1 3 DC 0V VC 7 0 VAB 1 5 VDD 10 0 DC 5V .MODEL MNMOS NMOS VTO=0.75, KP=25U + LAMBDA=0.01, GAMMA=0.8 PHI=0.6 .MODEL MPMOS PMOS VTO=-0.75 KP=8U +LAMBDA=0.02 GAMMA=0.4 PHI=0.6 .DC VAB -4.0 4.0 0.2 VC 2 5 1 .PRINT DC I(VSENSE) .PROBE .END Allen and Holberg - CMOS Analog Circuit Design Page V.2-7 THE SINGLE MOSFET DIFFERENTIAL RESISTOR VC i1 i1 R v1 v2 v2 - v1 i2 + v1 - - v1 v2 v2 + - i2 R VC Assume the MOSFET's are in the non-saturation region 1 i1 = β(V C - v 2 - V T )(v 1 - v 2 ) - 2 ( v 1 - v 2 ) 2 1 i2 = β(V C - v 2 - V T )(-v 1 - v 2 ) - ( -v 1 - v 2 ) 2 2 Rewrite as 1 i1 = β(V C - v 2 - V T )(v 1 - v 2 ) - ( v 1 2 - 2 v 1 v 2 + v 2 2 ) 2 1 i2 = β(V C - v 2 - V T )(-v 1 - v 2 ) - ( v 1 2 + 2 v 1 v 2 + v 2 2 ) 2 1 i1 - i2 = β(V C -v 2 -V T )(2v 1 ) - (v12-2v1v2+v22-v12-2v1v2-v22) 2 i1 - i 2 = 2β [ (VC - VT)v1 - 2v1v2 + 2v1v2 ] 2R = v1-(-v1) 2v1 2v1 1 = i -i = 2β(VC-VT)v = β(V -V ) i1-i2 12 1 CT or R= v1 ≤ V C - V T 1 W 2K L (VC-VT) Allen and Holberg - CMOS Analog Circuit Design Page V.2-8 Single-MOSFET, Differential Resistor Realization VC r ac/2 i1 i1 v2 v1 v2 v1 VCC r ac/2 - v1 v2 i2 - v1 v2 i2 R VC Voltage-Current Characteristics 1.0mA VC= 7V 6V 0.6mA 5V 4V 0.2mA ID(M1) 3V - 0.2mA - 0.6mA - 1.0mA -2 -1 0 V1 Single MOSFET Differential Resistor Realization M1 1 2 3 4 MNMOS1 W=15U L=3U M2 5 2 3 4 MNMOS1 W=15U L=3U VC 2 0 VCC 4 0 DC -5V V1 1 0 E1 5 0 1 0 -1 .MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6 .DC V1 -2.0 2.0 0.2 VC 3 7 1 .PRINT DC ID(M1) .PROBE .END 1 2 Allen and Holberg - CMOS Analog Circuit Design Page V.2-9 The Double MOSFET Differential Resistor VC1 i1 v1 iD2 iD1 i1 R v v1 v2 v + - + VC2 i2 R v v iD3 iD4 v2 VC1 i2 1 iD1 = β(V C1 -v-V T )(v1 -v) - 2(v1-v)2 1 iD2 = β(V C2 -v-V T )(v1 -v) - (v1-v)2 2 1 iD3 = β(V C1 -v-V T )(v2 -v) - (v2-v)2 2 1 iD4 = β(V C2 -v-V T )(v2 -v) - (v2-v)2 2 1 1 i1=iD1+iD3=β(VC1-v-VT)(v1-v)- (v1-v)2+(VC2-v-VT)(v2-v)- (v2-v)2 2 2 1 1 i2=iD2+iD4=β(VC2-v-VT)(v1-v)- (v1-v)2+(VC1-v-VT)(v2-V)- (v2-v)2 2 2 i1 - i 2 = β[(VC1-v-VT)(v 1-v) + (VC2-v-VT)(v 2-v) - (V C2-v-VT)(v1- v) - (VC1-v-VT)(v2-v)] = β[v1(VC1-VC2) + v 2(VC2-VC1)] = β(VC1-VC2)(v1-v2) v1-v2 v1-v2 1 = β(V -V )(v -v ) = KW i1-i2 C1 C2 1 2 (VC1-VC2) L 1 v1 ,v 2 ≤ min [(V C1-VT),(VC2-VT)] R i n = KW (VC1-VC2) L Rin = or Allen and Holberg - CMOS Analog Circuit Design Page V.2-10 Double-MOSFET, Differential Resistor Realization VC1 iD1 i1 M1 v3 v1 i1 iD2 r ac/2 v1 VSS v3 M2 r ac/2 v2 VC2 v4 i2 R iD3 M3 iD4 VSS v2 i2 M4 v4 VC1 Voltage-Current Characteristics 150uA VC2 = 6V 5V 100uA VBC =-5V V3 =0V VC1 =7V 50uA I(VSENSE) Double MOSFET Differential Resistor Realization M1 1 2 3 4 MNMOS1 W=3U L=3U M2 1 5 8 4 MNMOS1 W=3U L=3U M3 6 5 3 4 MNMOS1 W=3U L=3U M4 6 2 8 4 MNMOS1 W=3U L=3U VSENSE 3 8 DC 0 VC1 2 0 DC 7V VC2 5 0 VSS 4 0 DC -5V V12 1 6 .MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6 .DC V12 -3 3 0.2 VC2 2 6 1 .PRINT DC I(VSENSE)) .PROBE .END 4V 3V 2V 0 - 50uA - 100uA - 150uA -3 -2 -1 0 V1-V2 1 2 3 Allen and Holberg - CMOS Analog Circuit Design Page V.2-11 SUMMARY OF ACTIVE RESISTOR REALIZATIONS AC Resistance Realization Linearity How Controlled Restrictions Single MOSFET Poor V GS or W/L vBULK < Min (vS, v D) Parallel MOSFET Good VC or W/L v ≤ (VC - VT) Single-MOSFET, differential resistor Good VC or W/L Double-MOSFET, Very Good VC1 - V C2 or W/L differential resistor |v1| < VC - VT vBULK < -v1 Differential around v1 v1, v2 < min(VC1-VT, VC2-VT) vBULK < min(v1,v2) Transresistance only Allen and Holberg - CMOS Analog Circuit Design Page V.3-1 V.3 - CURRENT SINKS & SOURCES CHARACTERIZATION OF SOURCES & SINKS 1). Minimum voltage (vMIN) across sink or source for which the current is no longer constant. 2). Output resistance which is a measure of the "flatness" of the current sink or source. CMOS Current Sinks & Sources VDD VG = V GG iD iD VGG + v - vMIN v 0 iD VDD VG = V GG VGG iD + v 1 rOUT = λI D vMIN = vDS(SAT.) = vON vMIN 0 VDD 0 where vON = vGS - VT v Allen and Holberg - CMOS Analog Circuit Design Page V.3-2 SMALL SIGNAL MODEL FOR THE MOSFET G + D G B S gm = gmbs = 2K'WID L gm γ 2 2 φ F + | V BS | 1 1 r ds ≈ g = λI ds D vgs vbs S D B + - gmvgs gmbsvbs rds S Allen and Holberg - CMOS Analog Circuit Design Page V.3-3 INCREASING THE ROUT OF A CURRENT SOURCE MOS Circuit Small-Signal Model i OUT + iout + M2 r ds2 gm2 vgs2 vOUT + - r VGG - gmbs2 vbs2 + v S2 - r Loop equation: vout = [iout - (g m2vgs2 + gmbs2vbs2)]r ds2 + iout r But, v gs2 = -vs2 and vbs2 = - vs2. vout = [iout + gm2vs2 + gmbs2vs2]rds2 + iout r Replace vs2 by i outrvout = iout [ rds2 + gm2 rds2r + gmbs2rds2r + r ] Therefore, rout = rds2 + r [1 + gm2 rds2 + gmbs2rds2] MOS Small Signal Simplifications Normally, g m ≈ 1 0g mbs ≈ 1 00g d s Continuing rout ≅ rgm2 rds2 r out ≈ r x (voltage gain of M2 from source to drain) vout - Allen and Holberg - CMOS Analog Circuit Design Page V.3-4 CASCODE CURRENT SINK MOS Small-Signal Model Circuit iOUT IREF iout + M2 M4 + vOUT gmbs2vbs2 M3 M1 r ds2 gm2vgs2 vout - + vS2 - r ds1 gm1vgs1 - vout = [iout - (g m2vgs2 + g mbs2vbs2)]rds2 + ioutrds1 vout = iout[rds2 + gm2rds2r(1 + η2) + rds1] rout = rds2 + r[1 + g m2rds2(1 + η2)] ≅ r ds1gm2rds2(1 + η2) Note : v MIN = VT + 2VON ≅ 0.75 + 1.5 = 2.25 (assuming V ON ≈ VT) NMOS Cascode1mA Slope = 1/R o iO 0.75mA + + vGS2 - iO 0.5mA 0.25mA 0mA 0V VMIN 2V 4V vO 6V vO + vGS1 -8V 10V Allen and Holberg - CMOS Analog Circuit Design Page V.3-5 Gate-Source Matching Principle iD2 + iD1 iD2 + M1 - + vGS1 vGS2 vGS2 - M2 iD1 + S = W/L M2 vGS1 M1 - Assume that M1 and M2 are matched but may not have the same W/L ratios. 1). If vGS1 = vGS2, then iD1 = (S1/S2)iD2 a). v GS1 may be physically connected together , or b). v GS1 may be equal to vGS2 by some other means. 2). If i D1 = iD2, then a). vGS1 = VT + S2/S1(vGS2 - VT) , or b). If S1 = S2 and VS1 ≈ V S2 then vGS1 = vGS2 Strictly speaking, absolute matching requires that vDS be equal for two matched devices. Allen and Holberg - CMOS Analog Circuit Design Page V.3-6 Reduction of VMIN or VOUT (sat) High-Swing C ascode Method 1 for Reducing the Value of vOUT(sat) IREF IOUT 2VT + 2VON IOUT VOUT(sat) M4 M3 + VT + VON - + M2 VOUT M1 + VT + VON + VT + VON - - 0 VOUT VT + 2VON Standard Cascode Sink : vGS = VON + VT = Part of v G S t o achieve drain current Part of v G S t o enhance the channel + ∴ vDS(sat) = v GS - V T = (VON + VT) - VT = VON iD ID VT VT+VON Above is based on the Gate-Source matching principle. vGS Allen and Holberg - CMOS Analog Circuit Design Page V.3-7 Circuit Which Reduces the Value of Vout(sat) of the Cascode Current Sink iREF M6 M4 1/4 + - + 1/1 + VT + 2VON vOUT VT + VON - + 1/1 M2 + - 2VT + 3VON M5 1/1 VT + VON M3 iOUT iout iREF VT + 2VON M1 + VON 1/1 - VT + VON 1/1 - iD - W=1 L1 vOUT(sat) W =1 L4 VT + VON VT + 2VON ID 0 vOUT 2V ON K 'W iD = 2 (v - VT ) 2 L GS = 0 K 'W 2 2 L (V ON ) vGS VT Allen and Holberg - CMOS Analog Circuit Design Page V.3-8 Method 2 for Reducing VMIN for MOS Cascode Sink/Source iREF iREF iO 1 M5 M4 + 1/4 M1 VT + VON M2 + 1 + VON VT + VON 1 - - Assume (W/L)1 = (W/L)2 = (W/L)4 = 4(W/L)5 values are identical and ignore bulk effects. Let I = IO REF VGS1 = 2I REF + VT = VON + VT W1 K’ L 1 and V GS5 = 2I REF + VT W5 K’ L 5 Since (W/L)1 = 4(W/L)5 V GS5 = 2I REF + VT = 2 W1 K’ 4L 1 2I REF W1 K’ L 1 + V T = 2 VON + VT Allen and Holberg - CMOS Analog Circuit Design Page V.3-9 Since V GS3 = VGS4 = VON +VT VDS1 = V DS2 = V ON which gives a minimum output voltage while keeping all devices in saturation of v M I N = 2 VO N Output Plot: 1000µA ID(M4) 750µA 500µA 250µA 0µA 0V 1V 2V 3V VOUT 4V 5V Allen and Holberg - CMOS Analog Circuit Design Page V.3-10 Matching Improved by Adding M3 iREF iREF VT + M3 1 + - M4 + V T + VON 1/4 M1 VON 1 M5 + - iO V T + 2VON VT + V ON M2 V ON + 1 V T + V ON - + - 1 What is the purpose of M3? The presence of M3 forces the VDS1 = VDS2 which is necessary to guarantee that M1 and M2 act alike (e.g., both will have the same VT). Allen and Holberg - CMOS Analog Circuit Design Page V.3-11 CMOS REGULATED CASCODE CURRENT SOURCE Circuit Diagram VDD VDD iOUT IB2 RB2 M3 iD3 + vGS3 IB1 M4 vOUT Iout M2 M1 - VDS3 (min) VDS3 (sat) vDS3 Principle of operation: As v OUT decreases, M3 will enter the non-saturation region and iOUT will begin to decrease. However, this causes a decrease in the gatesource voltage of M4 which causes an increase in the gate voltage of M3. The minimum value of vOUT is determined by the gate-source voltage of M4 and Vdsat of M3. Assume that all devices are in saturation. vOUT(min) = 2IB2 K'(W/L)4 + 2Iout K'(W/L)3 + VT4 Allen and Holberg - CMOS Analog Circuit Design Page V.3-12 CMOS REGULATED CASCODE CURRENT SOURCE - CONT. Small Signal Model r ds3 iout + vgs3 + RB2 r ds4 gm4vgs4 vgs4 gm3vgs3 r ds2 - + vout - (Ignore bulk effects) iout = gm3vgs3 + g ds3(vout - v gs4) vgs4 = ioutrds2 vgs3 = vg3 - vs3 = -gm4(rds4||RB2)v gs4 - vgs4 = -rds2[1 + gm4(r ds4||RB2)]iout ∴ iout = -gm3rds2 [1 + gm4(rds4 ||RB2)]iout + g ds3 vout - gds3 rds2 iout Solving for vout, vout = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(r ds4||RB2)]iout vout rout = i = rds3[1 + gm3rds2 + gds3rds2 + gm3rds2gm4(r ds4||RB2)] out g m 2r3 r out = r ds3 g m3 r ds2 g m4 (r ds4 ||R B2 ) = 2 Example K' N = 25 µA/V2, λ = 0.01, IB1 = IB2 = 100µA, all transistors with minimum geometry (W = 3µm, L=3µm), and RB2 = rds, we get rds = 1MΩ and gm = 70.7µmho rout ≈ (1MΩ)(70.7µmho)((1MΩ)(70.7µmho)(1MΩ||1MΩ)= 2.5GΩ!!! Allen and Holberg - CMOS Analog Circuit Design Page V.3-13 CMOS REGULATED CASCODE CURRENT SOURCE - CONT. SPICE Simulation 160µA IB1=150µA 140µA 120µA IB1=125µA 100µA IB1=100µA iOUT 80µA 60µA IB1=75µA 40µA IB1=50µA 20µA 0µA 0 1 2 3 vOUT SPICE Input File CMOS Regulated Cascode Current Sink VDD 6 0 DC 5.0 IB1 6 4 DC 25U VOUT 1 0 DC 5.0 M1 4 4 0 0 MNMOS1 W=15U L=3U M2 3 4 0 0 MNMOS1 W=15U L=3U M3 1 2 3 0 MNMOS1 W=30U L=3U M4 2 3 0 0 MNMOS1 W=15U L=3U M5 5 4 0 0 MNMOS1 W=15U L=3U M6 5 5 6 6 MPMOS1 W=15U L=3U M7 2 5 6 6 MPMOS1 W=6U L=3U .MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6 .MODEL MPMOS1 PMOS VTO=-0.75 KP=8U +LAMBDA=0.02 GAMMA=0.4 PHI=0.6 .DC VOUT 5 0 0.1 IB1 50U 150U 25U .OP .PRINT DC ID(M3) .PROBE .END 4 5 Allen and Holberg - CMOS Analog Circuit Design Page V.3-14 SUMMARY OF CURRENT SINKS/SOURCES Current Sink/Source Simple Cascode High-Swing Cascode Regulated Cascode rOUT Minimum Voltage rd s VON ≈ gm2 rds2rds1 ≈ gm2 rds2rds1 VT + 2 VON ≈ gm 2rds3 VT + 2 VON 2 V ON Allen and Holberg - CMOS Analog Circuit Design Page V.4-1 V.4 - CURRENT MIRRORS/AMPLIFIERS What Is A Current Mirror/Amplifier ? Rout R in CURRENT iI iO MIRROR/ + vI Ideally, iO = A I iI Rin ≈ 0 + vO AMPLIFIER - Rout ≈ ∞ Graphical Characterization iI iO slope = 1/Rin slope = 1/Rout II IO vI vMIN INPUT vO vMIN OUTPUT iO AI 1 iI TRANSFER Allen and Holberg - CMOS Analog Circuit Design Page V.4-2 CURRENT MIRROR AND CURRENT AMPLIFIERS Sources of E rrors iI CURRENT iI iO MIRROR/ AMPLIFIER + + vDS1 M1 - In general, iO W2L1 v GS - V T 2 2 iI = W1L2v GS - V T 1 iO 1+λvDS2 µo2Cox2 1+λvDS1 µo1Cox1 If the devices are matched, iO W2L1 1+λvDS2 = W L 1+λv iI DS1 1 2 If vDS1 = vDS2, W 2L 1 iO iI = W1L2 Therefore the sources of error are: 1). v DS1 ≠ vDS2 2). M1 and M2 not matched (∆β and ∆VT) + vGS - M2 vDS2 - Allen and Holberg - CMOS Analog Circuit Design Page V.4-3 Simple Current Mirror With λ ≠ 0 DS1 M2 + vGS - + v DS2 - ( 1 + λv M1 v SS Ratio Error vDS1 - 10 λ = 0.02 8 1 + λv DS2 iO iI + - 1)x100% Circuit - λ = 0.015 6 4 λ = 0.01 2 0 0V 1V 2V 3V VDS1-VDS2 4V Ratio error (%) versus drain voltage difference Used to measure λ iO 1+ λ v D S 2 S1 = 1+ λ v iI D S 1 S2 If S 1 = S 2, v DS2 = 10V, vDS1 = 1V, and i O/iI = 1.501, then iO 1+10λ ∴ = 1.501 = 1+ λ iI 0 .5 ---> λ = 8.5 = 0.059 5V Allen and Holberg - CMOS Analog Circuit Design Page V.4-4 Matching Accuracy of MOS Current M irrors Neglect λ effects iD1 iD2 + M1 Define: + vGS1 vGS2 M2 (vDS2 > vGS2 - VT1) - ∆β = β2 - β1 iO = iD2 = β2(vGS2-VT2)2 iI iD1 β1(vGS1-VT1)2 and ∆VT = V T2 - V T1 and β1 + β2 2 VT1+VT2 VT = 2 β= ∆VT ∆β ∆β , β 2 = β + 2 , VT1 = VT - 2 2 ∆VT and V T2 = V T + 2 ∴ β1 = β - Thus, ∆ V T2 ∆β β+ v GS - vT iO 2 2 ∆ V T 2 iI = ∆β β - v GS - v T + 2 2 = T 1-2(v∆V-V ) 2 GS T ∆V T ∆β 1 1+ 2β 2(vGS-VT) ∆β 1 + 2β ∆VT ∆VT 2 iO ∆β ∆β iI ≈ 1+ 2β 1+ 2β 1-2(vGS-VT)1-2(vGS-VT) 2∆VT iO ∆β iI ≈ 1 + β - (v GS - V T ) , ∆V T ∆β ± ≈ 5% , (v = ± 10% β GS - V T ) iO ∴ iI ≈ 1 ± 0.05 - (± 0.2) = 1 ± 0.15 = 1 ± 0.25 if β and VT are correlated Allen and Holberg - CMOS Analog Circuit Design Page V.4-5 Matching Accuracy - Continued RATIO ERROR ( iO - 1)100% iI Illustration 7 6 II = 1uA 5 4 3 II = 5uA 2 II = 10uA 1 II = 50uA 1 2 3 4 5 6 ∆ VT(mV) 7 8 9 10 Allen and Holberg - CMOS Analog Circuit Design Page V.4-6 Layout Techniques to Remove Layout E rror Layout without correction technique iI iO iI M1 iO M2 M2 V SS VSS Layou t with correction technique iI iO iI M1 M2 a M2 b M2 c M2 d M2 e M1 iO M2 a M2 b VSS VSS M2 c M2 d M2 e Allen and Holberg - CMOS Analog Circuit Design Page V.4-7 Practical Current Mirrors/Amplifiers • Simple mirror • Cascode current mirror • Wilson current mirror Simple Current Mirror iI = 60uA 60uA Current mirrors and amplifiers .MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6 M1 1 1 0 0 MNMOS1 W=3U L=3U M2 3 1 0 0 MNMOS1 W=3U L=3U IIN 0 1 VOUT 3 0 .DC VOUT 0 5 0.1 +IIN 0 60U 10U .PRINT DC ID(M2) .PROBE .END iI = 50uA iI = 40uA 40uA iI = 30uA iOUT iI = 20uA 20uA iI = 10uA 0 0 1 2 3 4 5 vOUT iI iO 3u 3u 3u 3u M1 M2 + vO - Allen and Holberg - CMOS Analog Circuit Design Page V.4-8 Cadcode Current Mirror CIRCUIT SPICE iOUT iI M3 60uA M4 40uA iOUT mproved current mirror .MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6 M1 1 1 0 0 MNMOS1 W=3U L=3U M2 2 1 0 0 MNMOS1 W=3U L=3U M3 3 3 1 0 MNMOS1 W=3U L=3U M4 4 3 2 0 MNMOS1 W=3U L=3U IIN 0 3 VOUT 4 0 .DC VOUT 0 5 0.1 + IIN 10U 60U 10U .PRINT DC ID(M4) .PROBE .END iI = 60uA iI = 50uA iI = 40uA iI = 30uA iI = 20uA 20uA M1 M2 iI = 10uA 0 VSS 0 1 2 3 4 5 vOUT Example of Small Signal Output Resistance Calculation ii io + v3 - + rds3 gm3 v3 v4 - + rds4 v1 =v3 =0 + v1 - 1). 2). 3). gm4 (v3 +v1 -v2 ) io + rds1 gm1 v1 v2 - rds2 gm2 v1 gmbs v2 vo - vo = v4 + v2 = rds4 [i o - gm4(v 3 + v1 - v2) + gmbs4v2] + rds2(io - gm2v1) v 2 = iords2 v o = io [rds4 + (gm4 rds2)rds4 + (rds2gmbs4)rds4 + rds2] vo 4). rout = io = rds4 + rds2 + rds2rds4(gm4 + gmbs4 ) Allen and Holberg - CMOS Analog Circuit Design Page V.4-9 Wilson Current M irror Circuit and PerformanceIin = 80uA iI M3 70uA 65.5uA iO 60uA 50uA 45.0uA M1 M2 VSS 40uA iO 30uA 22.5uA 20uA 10uA 0 0 Wilson Current Source M1 1 2 0 0 MNMOS W=15U L=3U M2 2 2 0 0 MNMOS W=15U L=3U M3 3 1 2 0 MNMOS W=15U L=3U R 1 0 100MEG .MODEL MNMOS NMOS VTO=0.75, KP=25U, +LAMBDA=0.01, GAMMA=0.8 PHI=0.6 IIN 0 1 VOUT 3 0 .DC VOUT 0 5 0.1 IIN 10U 80U 10U .PRINT DC V(2) V(1) ID(M3) .PROBE .END 1 2 3 4 5 vOUT Principle of Operation: Series negative feedback increase output resistance 1. Assume input current is constant and that there is high resistance to ground from the gate of M3 or drain of M1. 2. A positive increase in output current causes an increase in vGS2 . 3. The increase in vGS2 causes an increase in vGS1 . 4. The increase in vGS1 causes an increase in iD1. 5. If the input current is constant, then the current through the resistance to ground from the gate of M3 or the drain of M1 decreases resulting in a decrease in vGS3. 6. A decrease in v GS3 causes a decrease in the output current opposing the assumed increase in step 2. Allen and Holberg - CMOS Analog Circuit Design Page V.4-10 Output Impedance of the Wilson Current Source iout + iin=0 v3 + rds3 gm3(v1-v2) - gm1v2 rds1 + v1 - rds2 gm2v2 + v2 - gmbs3v2 vout - vout = rds3[iout - gm3v1 + gm3v2 + gmbs3v2] + v2 vout = rds3iout - gm3rds3(-gm1rds1v2) + gm3rds3v2 + gmbs3rds3v2 + v2 rds2 v2 = iout 1 + g m2 r d s 2 vout = ioutrds3 + [gm3rds3 + gmbs3rds3 + gm1rds1gm3rds3]v2 + v2 1 + g m3 r ds3 + g mbs3 r ds3 + g m1 r ds1 g m3 r ds3 1+gm2rds2 rout = rds3 + rds2 r ds2 g m1 r ds1 g m3 r ds3 r out ≈ ≈ r ds1 × ( g m 3 r ds3 ) if g m 1 = g m 2 gm2rds2 Allen and Holberg - CMOS Analog Circuit Design Page V.4-11 Improved Wilson Current M irror Iout Iin M1 M4 M3 Additional diode-connected transistor equalizes the drain-source voltage drops of transistors M2 and M3 M2 SPICE simulation improved Wilson current source .MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6 M1 1 2 3 0 MNMOS1 W=12U L=3U M2 3 3 0 0 MNMOS1 W=12U L=3U M3 5 3 0 0 MNMOS1 W=12U L=3U M4 2 2 5 0 MNMOS1 W=12U L=3U .DC VOUT 0 5 0.2 IIN 10U 80U 10U R 2 0 100MEG IIN 0 2 VOUT 1 0 .PROBE .PRINT DC ID(M1) .END 77.5uA 45.0uA Iout Iin = 80uA 70uA 60uA 50uA 40uA 30uA 20uA 22.5uA 10uA 0 1 2 3 Vout 4 5 Allen and Holberg - CMOS Analog Circuit Design Page V.4-12 Regulated Cascode Current M irror VDD iOUT IB M4 + IIN M3 vOUT + vGS4 - M1 M2 - VSS Small Signal Equivalent Model (gmbs effects ignored) iout + rds4 gm4vgs4 v4 + g m3 v3 rds3 rds2 vout v3 - - vout = (iout - gm4vgs4)rds4 + ioutrds2 vgs4 = v 4 - v 3 v3 = ioutrds2 v4 = -gm3v3rds3 vout = ioutrds4 - gm4(-gm3ioutrds2rds3 - ioutrds2)r ds4 + ioutrds2 rout = rds4 + gm4 g m3 r ds2rds3rds4 + rds2 + gm4 rds2rds4 vOUT(min) = 2IB K'(W/L)4 + 2Iout K'(W/L)3 + VT4 Allen and Holberg - CMOS Analog Circuit Design Page V.4-13 SUMMARY OF CURRENT MIRRORS Accuracy Output Resistance Minimum Voltage Simple Poor (Lambda) r ds VON Cascode Excellent g m rds2 VT + 2V ON Wilson Excellent g m rds2 2VON Good gm 2rds3 VT + 2VON Current Mirror Regulated Cascode Allen and Holberg - CMOS Analog Circuit Design Page V.5-1 V.5 - REFERENCE CIRCUITS Introduction What is a Reference Circuit? A reference circuit is an independent voltage or current source which has a high degree of precision and stability. Requirements for a Reference Circuit 1 .) Output voltage/current should be independent of power supply. 2.) Output voltage/current should be independent of temperature. 3.) Output voltage/current should be independent of processing variations. V-I Characteristics of an Ideal Reference i Voltage Reference Iref Current Reference Vref v Allen and Holberg - CMOS Analog Circuit Design Page V.5-2 Concept of Sensitivity Definition Sensitivity is a measure of dependence of Vref (Iref) upon a parameter or variable x which influences Vref (Iref). Vref S x ∂Vref Vref x ∂Vref = = ∂x Vref ∂x x where x = VDD or temperature Application of Sensitivity V ∂Vref ref ∂x Vref = x x S For example, if the sensitivity is 1, then a 10% change in x will cause a 10% change in V ref. Vref Ideally, S x →0 Allen and Holberg - CMOS Analog Circuit Design V .5-1 - SIMPLE R EFERENCES Objective is to minimize, Vref S V DD = ∂Vref Vref ∂VD D VDD Types of references include, 1. Voltage dividers - passive and active. 2. MOS diode reference. 3. PN junction diode reference. 4. Gate-source threshold referenced circuit. 5. Base-emitter referenced circuit. Page V.5-3 Allen and Holberg - CMOS Analog Circuit Design Page V.5-4 Passive Divider Accuracy is approximately equivalent to 6 bits (1/64). VDD RA V1 I RB V2 RC VSS Active Dividers I V3 M3 VDD VDD V2 M2 M2 V1 M1 M2 + M1 Vref - + M1 Vref - Allen and Holberg - CMOS Analog Circuit Design Page V.5-5 PN Junction Voltage References VCC kT I I VREF = VBE = q ln = Vt ln I I s s I R V CC - V B E VCC ≈R If I = R + VREF VCC V REF ≈ V t ln RI - s Sensitivity: VREF S = V CC 1 VCC ln RI s VREF If VCC = 10V, R = 10 kΩ, and Is = 10-15A, then S = 0.0362. V CC Modifying the Value of VR EF VCC R IR1 R1 If β >> 1, then VREF ≈ IR1 (R 1+R2) I + VREF R2 - VBE replacing IR1by R1 gives, R 1 +R2 VREF ≈ V BE R1 or R1+R2 VCC V REF ≈ Vt ln R1 RIs Allen and Holberg - CMOS Analog Circuit Design Page V.5-6 Gate-Source Referenced Circuits (MOS equivalent of the pn junction referenced circuit) VDD 2(VDD-V REF) βR VREF = VGS = VT + I R 1 V REF = VT − βR + + 2(VDD-VT) 1 + 22 βR βR VREF Sensitivity: - V REF S VDD VDD 1 =V 1 + β R(V REF REF - V T ) If V DD = 10V, W/L = 10, R = 100kΩ and using the results of Table 3.1-2 gives VREF VREF = 1.97V.and S = 0.29. VDD Modifying the Value of VR EF V DD R IR1 R1 R 1 +R2 V GS R2 VREF ≈ I + V REF R2 - Allen and Holberg - CMOS Analog Circuit Design Page V.5-7 Bootstrapped Current Source VDD M4 M5 M3 RB ID1 = I1 iOUT ID2 = I2 M6 M2 M8 M1 R I2 Principle: If M3 = M4, then I 1 = I2 (1) also, VGS1 = VT1 + 2I1 KNS1 = I2R therefore, VT1 1 I2 = R + R 2I1 KNS1 Desired operating point Eq. (2) Eq. (1) (2) Undesired operating point Allen and Holberg - CMOS Analog Circuit Design Page V.5-8 Bootstrapped Current Sink/Source - Continued An examination of the second-order effects of this circuitThe relationship between M1 and R can be expressed as, I2R = VT1 + 2I1 β1 Instead of assuming that I1 = I2 because of the current mirror, M3-M4, let us consider the effects of the channel modulation which gives 1 + λPV G S 4 I 2 = I1 1 + λ P (V D D - V DS1 ) Solving for I1 from the above two expressions gives I1R(1 + λPVGS4) = [1 + λP(V DD-V DS1)] 2I1 β1 Differentiating with respect to VDD and assuming the VDS1 and VGS4 a re constant gives (IOUT = I1), 20VDD λPV T1 + IOUT S VDD = IOUTR(1 + λ P V GS4 ) 2I1 β1 1 + λ P (V D D - V DS1 ) 2 β 1I1 Allen and Holberg - CMOS Analog Circuit Design Page V.5-9 Bootstrapped Current Sink/Source - Continued Assume that VDD =5V, K N ' = 23.6 µA/V2, VTN=0.79V, γN=0.53V0.5, φ P = 0.590V, λN=0.02V-1, K P ' = 5.8µA/V2, VTP=-0.52V, γP=0.67V0.5, φ P = 0.6V, λN=0.012V-1. Therefore, VGS4 = 1.50V, VT2 = 1.085V, VGS2 = 1.545V, and VDS1 = 2.795V which gives IOUT S VDD ∆IOUT/IOUT = 0.08 = ∆V /V DD DD ∆ V DD = 3.2µA If ∆VDD = 6V - 4V = 2V, then ∆IOUT = 0.08 I OUT V DD SPICE Results: 120µA 100µA ∆ IOUT ≈ 2.8µA for ∆ VDD 4V →6V 80µA IOUT 60µA 40µA 20µA 0µA 0V 2V 4V VDD 6V 8V 10V Allen and Holberg - CMOS Analog Circuit Design Page V.5-10 Base-Emitter Voltage Referenced Circuit VDD M4 M5 M3 RB ID1 = I1 ID2 = I2 M6 M1 M8 I2 ≈ VBE1 R = I5 V = I2R ≈ V BE1 Q1 M2 R iOUT Allen and Holberg - CMOS Analog Circuit Design Page V.5-11 V .5-2 - TEMPERATURE D EPENDENCE Objective Minimize the fractional temperature coefficient which is defined as 1 ∂Vref T CF = V ∂ T parts per million per °C or ppm/°C ref Temperature Variation of References PN Junction: v i ≈ I s exp V t -V GO I s = K T 3 e xp V t ∂I 1 s Is ∂ T = ∂ (ln I s ) 3 V GO V GO = T + TV ≈ TV ∂T t t dvBE V BE - V G O = -2mV/°C at room temperature dT ≈ T (VGO = 1.205 V and is called the bandgap voltage) Gate-Source Voltage with constant current (Strong Inversion): dVGS dVT dT = dT + 2L d WCox dT ID µ o µo = KT-1.5 ; VT = VT0 - αT or VT(T) = VT(To) - α(T-To) dV G S 3 = -α + 4 dT V GS - V T T Allen and Holberg - CMOS Analog Circuit Design Page V.5-12 PN Junction Voltage Reference VDD R I + VREF = VBE = kT ln I = Vt ln I q Is Is - V DD - v B E V DD I= ≈R R TCF = -------> VDD V REF = V t l n RI s dV REF V REF - V G O VREF dT = TVREF 1 Vt dR -V REF RdT Assume VREF = 0.6 volts and that R is a polysilicon resistor dR = + 1500 ppm/ ° C gives a RdT 0 .6 - 1.205 0 .026 TC F = (300K)(0.6) - 0.6 (0.0015) = -0.003361 - 0.000065 = -3426 ppm/°C Allen and Holberg - CMOS Analog Circuit Design Page V.5-13 Gate - Source Referenced Circuits MOS Equivalent of the PN Junction Referenced Circuit VDD R I + VREF - 1 V R E F = V T − βR + 1 d V REF = TCF = V REF dT 2(VDD−VT) 1 + 22 βR βR 1 VREF V DD − V REF 1.5 1 d R − R dT 2βR T 1 1+ 2 β R (V DD − V REF ) −α + Allen and Holberg - CMOS Analog Circuit Design Page V.5-14 Example W = 2L, VDD = 5V, R = 100 KΩ , K’=110 µ , VT = 0.7, T = 300 K, α = 2.3 mV/°C Solving for VREF gives VREF = 1.281 V dR = +1500 ppm/°C RdT −2.3× 10-3 + 1 dV REF 1 TCF = 1.281 dT = 1.281 TCF = - 928 ppm/°C 1+ 5 − 1.281 1.5 − 1500 × 10-6 300 2 × 2 110×10-6 × 100K 1 2 × 2 110×10-6 × 100K (5 - 1.281) Allen and Holberg - CMOS Analog Circuit Design Page V.5-15 Bootstrapped Current Source/Sink VDD M4 M5 M3 RB I D1 = I1 I D2 = I2 iOUT M6 M2 M8 M1 R 2ID1 L + VT VGS1 V ON + V T K'W ID2 = R = = = ID1 = IOUT R R Assuming that VON is constant as a function of temperature because of the bootstrapped current reference, then ∴ TCF = 1 dVT 1 dR -α 1 dR - R dT = V - R dT VT dT T If R is a polysilicon resistor, then -2.3 x 10 -3 - 1.5x10 -3 = -3800 ppm/°C 1 If R is an implanted resistor, then TC F = TC F = - 2.3 x 10 -3 - 0.4x10-3 = -2700 ppm/°C 1 Allen and Holberg - CMOS Analog Circuit Design Page V.5-16 Base-Emitter Voltage - Referenced Circuit VDD M4 M5 M3 RB ID1 = I1 ID2 = I2 iOUT M6 M1 M8 Q1 vBE1 I2 ≈ R M2 R 1 dv BE 1 dR -----> TCF = v - R dT BE dT Assuming VBE = 0.6 volts and a polysilicon resistor gives 1 TCF = 0.6 (-2x10-3) - (1.5x10-3) = -4833 ppm/°C Allen and Holberg - CMOS Analog Circuit Design Page V.6-1 V.6 - SUMMARY • The circuits in this chapter represent the first level of building blocks in analog circuit design. • The MOS transistor makes a good switch and a variable resistor with reasonable ranges of linearity in certain applications. • Primary switch imperfection is clock feedthrough. In order for switches to be used with lower power supplies, VT must be decreased. • The primary characteristics defining a current sink or source are VMIN and Rout. V MIN → 0 and Rout → ∞. Typically the product of VMIN times Rout is a constant in most designs. • Current mirrors are characterized by: Gain accuracy Gain linearity VMIN on output Rout Rin • Reasonably good power supply independent and temperature independent voltage and current references are possible. These references do not satisfy very stable reference requirements. Allen and Holberg - CMOS Analog Circuit Design Page VI.0-1 VI. CMOS AMPLIFIERS Contents VI.1 Simple Inverting Amplifier VI.2 Differential Amplifiers VI.3 Cascode Amplifier VI.4 Output Amplifiers VI.5 Summary Organization Chapter 10 D/A and A/D Converters Chapter 11 Analog Systems SYSTEMS Chapter 7 CMOS Comparators Chapter 8 Simple CMOS OTA's Chapter 9 High Performance OTA's COMPLEX CIRCUITS Chapter 5 CMOS Subcircuits Chapter 6 CMOS Amplifiers SIMPLE Chapter 2 CMOS Technology DEVICES Chapter 3 CMOS Device Modeling Chapter 4 Device Characterization Allen and Holberg - CMOS Analog Circuit Design Page VI.1-1 VI.1 SIMPLE INVERTING AMPLIFIERS CHARACTERIZATION OF AMPLIFIERS We shall characterize the amplifiers of this Chapter by the following aspects: • Large Signal Voltage Transfer Characteristics • Maximum Signal Swing Limits • Small Signal Midband Performance Gain Input resistance Output resistance • Small Signal Frequency Response • Other Considerations Noise Power Etc. Allen and Holberg - CMOS Analog Circuit Design Page VI.1-2 VI.1.1 - CMOS INVERTERS Types VDD VGG2 M2 M2 + M1 + vIN - M2 + M1 vOUT + vIN Active Current Load Source Inverter Inverter + vOUT vIN - + M1 - vOUT Push-pull inverter Allen and Holberg - CMOS Analog Circuit Design Page VI.1-3 ACTIVE LOAD INVERTER - VOLTAGE TRANSFER CURVE CMOS Active Load Inverter VDD 3 0 DC 5.0 5V 1.2 v IN=5V M2 iD (mA) 0.8 vIN =4V 0.6 0.4 W1 15µ m = L1 3µm M1 vIN =3.5V vIN=3V v IN - vIN=1V v IN=2V vIN =1.5V 0 1 2 v OUT 3 4 + vOUT + vIN=2.5V 0.2 0 W2 15µ m = L2 3µm vIN=4.5V 1.0 - 5 5 4 3 vOUT 2 1 0 0 1 2 v IN 3 4 SPICE Input File: VIN 1 0 DC 0.0 M1 2 1 0 0 MNMOS1 W=15U L=3U M2 2 2 3 3 MPMOS1 W=15U L=3U .MODEL MNMOS1 NMOS VTO=0.75 KP=25U LAMBDA=0.01 GAMMA=0.8 PHI=0.6 .MODEL MPMOS1 PMOS VTO=-0.75 KP=8U LAMBDA=0.02 GAMMA=0.4 PHI=0.6 .DC VIN 0 5 0.1 .OP .PRINT DC V(2) .PROBE .END 5 Allen and Holberg - CMOS Analog Circuit Design Page VI.1-4 Active Load CMOS Inverter Output Swing Limits Maximum: vIN =0 ⇒ iD=0 ⇒ vSD2=|VT2 | VDD M2 iD ∴ v OUT (max) ≈ V DD − | V TP | Minimum: Assume v IN = VDD, M1 active, M2 saturated, and VT1 = VT2 = VT. vDS1 2 (v M1: iD = β1 GS1 −VT)vDS1 − 2 vOUT vIN M1 VSS (v OUT−VSS)2 (V = β 1 DD−VSS−VT)(vOUT−VSS)− 2 β2 β β 2 = 2(V −v 2 = 2(v 2 M2: iD = 2 (vGS −VT) 2 DD OUT−VT) 2 OUT+VT−VDD) β2 iD = 2 (vOUT −VSS+VSS+VT−VDD)2 β2 = 2 (vOUT−VSS)−(VDD −VSS−VT)2 Define vOUT' = vOUT − V SS and VX = VDD − V SS − V T (vOUT')2 V v ∴ iD = β1 X OUT '− (M1) 2 β2 iD = 2 v OUT ' − V X 2 (M2) Equate currents v OUT '2 β2 2 2 2 v OUT ' − 2 V X v OUT ' + V X = β1V X v OUT ' − 2 β2 2 2 2 or β1v OUT ' − 2 V X v OUT ' + V X = 2VX vOUT' − v OUT ' β2 β2 β2 2 1 + vOUT '2 − 2VX 1 + vOUT ' + β 1 β 1 β1 V X = 0 β 2 /β 1 2 − 2V v 2 vOUT' X OUT ' + 1+β /β VX = 0 2 1 Allen and Holberg - CMOS Analog Circuit Design β 2 /β 1 1 − 1+β2/β1 = VX 1 − V D D − V SS − V T v O U T (min.) = V D D − V T − 1 + β 2 /β 1 ∴ vOUT' = VX1 ± Page VI.1-5 1 1 + β 2 /β 1 Allen and Holberg - CMOS Analog Circuit Design Page VI.1-6 Interpretation of vOUT(min.) vOUT(min.) = (VDD − V SS − V T)1 − 1 β2 1+ β 1 + VSS VDD = −VSS = 5V VT = 1V vOUT 5 3 v MAX 1 0 0.1 1 10 -1 v MIN -3 -5 Gain ~ β1 β2 β1 β2 Allen and Holberg - CMOS Analog Circuit Design Page VI.1-7 Active Load I nverters Small Signal Characteristics Model: 5V S2=B2 gm2 vgs2 M2 + M1 v OUT + vIN - rds2 D1=D2=G2 G1 + v in gm1 vin r ds1 v out v in g m1 v in - - + + + r ds1 g m2 v out rds2 v out - - S1=B1 - Small Signal Voltage Gain vout = −g m1 v in + g m2 v outr ds1 | | r d s 2 −gm1 − g m1 vout =g ≈g =− vin ds1 + g ds2 + g m 2 m2 W1 2KN L I1 1 W2 2KP L I2 =− 2 vout vin = − If K N ' W1L2 =− K P ' W2L1 µNO W1L2 µPO W2L1 vout W 1/L1 = 20, then v = −6.67 using the parameters of Table 3.1-2 W2/L2 in Small Signal Output Resistance 1 1 rout = g ≈g ds1 + g ds2 + g m 2 m2 β1 β2 Allen and Holberg - CMOS Analog Circuit Design Page VI.1-8 High Gain CMOS Inverters VDD VGG VDD M2 M2 I I vIN vOUT vIN vOUT M1 M1 V SS V SS Inverter with current source load Push-pull, inverter I M2 vIN = V SS M1 vIN = VDD .8V SS .8V DD .6V SS .6V DD .4VSS .2VSS 0 .2VDD .4VDD VSS .4V DD I J K .2VDD H G F=F' 0 D' E' E D G' K' J' I' H' .5VSS 0 .5VDD C=C' .2V SS B=B'.4V SS .6V SS A=A' V DD vOUT Large signal transfer characteristics of inverter with a current source and push pull inverter Allen and Holberg - CMOS Analog Circuit Design Page VI.1-9 High Gain, CMOS Inverter Large Signal Transfer Characteristics vOUT C' A=A' B ≅ B' M1 sat. M2 non-sat. C E' D VSD2 > VSG2 - VT2 VDD - v OUT > VDD - VGG - VT2 v OUT < VGG + VT2 .8VDD vOUT = vin - VT1 M1 & M2 saturated .6VDD E M1 non-sat. M2 sat. .4VDD M2 non-sat. vout = VGG + VT2 .2V DD M2 sat. VSS vOUT = vin + VT2 VDD D' VGG = 0 F=F' .8VSS .6VSS .4VSS .2VSS 0 .2VDD .4VDD .6VDD .8VDD VDD v IN .2VSS .4VSS G H I .6VSS .8VSS VDS1 > VGS1 - VT1 v OUT - VSS > v IN - VSS - VT1 v OUT > v IN - VT1 VSS J K G' H' I' J' K' Advantages: 1. High gain. 2. Large output signal swing. 3. Large current sink and source capability in push pull inverter. Allen and Holberg - CMOS Analog Circuit Design Page VI.1-10 CMOS Inverter Characteristics Circuit: VDD M2 I vIN vOUT M1 VSS PSPICE Characteristics: 6 M2 linear 4 2 v OUT M2 saturated Current in M1 or M2 100 µA M1 linear voltage transfer curve 0 -2 vIN + VT2 M1 off M2 linear CMOS inverter DC current and sweep VIN 1 0 VDD 3 0 DC 5.0 VSS 4 0 DC -5.0 M1 2 1 4 4 MNMOS1 W=3U L=3U M2 2 1 3 3 MPMOS1 W=9U L=3U .MODEL MNMOS1 NMOS VTO=0.75 KP=25U +LAMBDA=0.01 GAMMA=0.8 PHI=0.6 .MODEL MPMOS1 PMOS VTO=-0.75 KP=8U +LAMBDA=0.02 GAMMA=0.4 PHI=0.6 .DC VIN -5.0 5.0 0.1 .PRINT DC V(2) ID(M1) .PROBE .END M1 saturated M1 linear vIN - VT2 -4 0 µA M2 off -6 -5 -3 -1 0 vIN 1 3 5 Allen and Holberg - CMOS Analog Circuit Design Page VI.1-11 Current Source Inverter - Output Swing Limits VDD VGG M2 I vOUT vIN M1 VSS v OUT(max.) ≈ V D D β2 VDD−VGG−VT2 1 − β V −V −V SS T1 1 DD vOUT(min.) = VDD − V T1− (V DD − V SS− V T1) CMOS Push - Pull Inverter - Output Swing Limits VDD M2 I vIN vOUT M1 v OUT(max.) ≈ V D D v OUT(min.) ≈ V SS VSS Allen and Holberg - CMOS Analog Circuit Design Page VI.1-12 High Gain, CMOS Inverters Small Signal Characteristics Model + + gm1vin vin r ds1 gm2vin r ds2 vout - - Small Signal Voltage Gain: vOUT = −g m1 v in + g m2 v inr ds1 | | r ds2 OR vout − g m1 + g m 2 = = vin g ds1 + g ds2 − 2 I D W1 KN' L + 1 λ1 + λ2 W2 KP' L 2 = K ! !! ID Set g m2 = 0 for the current source inverter W1 W2 Assume that iD = 1 µA and L1 = L2 , using the values of Table 3.1-2 gives vOUT vin = − 328 = −194 for the push-pull inverter (L=10 µm) for the current source inverter (L=10 µm) Small Signal Output Resistance: rout = 1 g ds1 + g ds2 Allen and Holberg - CMOS Analog Circuit Design Page VI.1-13 High Gain, CMOS Inverters Dependence of Gain upon Bias Current log AV 1000 100 weak inversion strong inversion 10 1 0.1µA 1µA 10µA 100µA 1000µA ID Limit is the subthreshold current where square law characteristic turns into an exponential characteristic. Assume that the level where subthreshold effects begin is approximately 0.1µA, the maximum gains of the CMOS inverters become: The CMOS inverters become: Push-Pull: -1036 Current source load: -615 Current sink load: -422 W = 1, L=10 µm L Allen and Holberg - CMOS Analog Circuit Design Page VI.1-14 Frequency Response of CMOS Inverters General Configuration X = vOUT ; Active Load CMOS Inverter (gm = gm1 ) X = VGG ; CMOS Inverter with a Current Source Load (g m = gm1) X = v IN ; CMOS Push Pull Inverter (gm = gm1 + gm2) VDD C GS2 C GD1 X C GD2 M2 C BD2 + vin CGD1 v in C BD1 CL + g m vin R CT v out - - M1 VSS (b) (a) (a) General configuration of an inverter illustrating parasitic capacitances. (b) Small signal model of (a) CGD1 and CGD2 are overlap capacitances CBD1 and C BD2 are the bulk-drain capacitances CL is the load capacitance seen by the inverter Frequency Response vOUT − g m R ω 1(1− s/z) , vIN = s + ω 1 1 ω 1 = RC gm and z = C GD1 1 (gm2 = 0 for push pull and current source inverters) R = g +g +g ds1 ds2 m2 C ≈ CGD1+CGS2+CBD1+CBD2+CL (Active load inverter) C ≈ CGD1+CGD2+CBD1+CBD2+CL (Current source & push-pull inverter) if g mR >> 1 Allen and Holberg - CMOS Analog Circuit Design Page VI.1-15 Frequency Response of CMOS Inverters Dependence of Frequency Response on Bias Current When g m2 ≠ 0 (active load inverter): W 2K' L I D 1 R≈g or ω -3dB = ~ ID C m2 When gm2 = 0 (push pull and current source inverter): (λ 1 + λ 2 ) ID 1 R = (λ or ω -3dB = ~ ID C 1 + λ 2 ) ID Example: Find the −3dB frequency for the CMOS inverter using a current source load and the CMOS push pull inverter assuming that iD = 1µA, CGD1=CGD2=0.2pF and CBD1=CBD2=0.5pF W1 W2 Using the parameters of Table 3.1-2 and assuming that L1 = L2 = 1 Gives, For the active load CMOS inverter, gm2 ω-3dB = C = 3.124x10 -6 rads/sec or 512KHz For the push pull or current source CMOS inverter, g gd1 + g ds2 ω -3dB = = 14.3x10 3 rads/sec or 2.27 KHz C gm1 z=C = 29.155 Mrads/sec or 4.64 MHz GD1 The reason for the difference is the higher output resistance of the push pull or current source CMOS inverters Allen and Holberg - CMOS Analog Circuit Design Page VI.1-16 NOISE IN MOS INVERTERS Noise Calculation RL RS i2 d v IN + RL i2 L RS - 2 We wish to determine the equivalent input noise voltage, vn as shown below: RL v2 n RS 8 2 id = KTg m (A2/Hz) 3 4 KT 2 2 iL = RL (A /Hz) Comments: 1.) 1/f noise has been ignored. 2.) Resistors are noise-free, they are used to show topological aspects. Can repeat the noise analysis for the resistors if desired. Allen and Holberg - CMOS Analog Circuit Design Page VI.1-17 Noise in an Active Load Inverter VDD e2 n2 M2 2 eout vOUT vIN eout e2 n1 2 eeq = vIN=0 2 gm1 2 2 + en2 gm2 = en1 2 M1 gm2 2 2 2 2 eeq = g = en1 +g en2 m1 2 m1 VSS 2 en1 1 gm2 2 gm2 2 en2 + g m1 e2 n1 Sec 3.2, Eq (15) B 2 en = fWL ; B=constant for a process 1/f noise: Sec. 3.3, Eq (6) 2 K' W gm = ID L So 2 eeq = 2 en1 1 ' W2 2KP ID L2 BP fW1L1 + W1 fW2L2 BN ' 2KN ID L1 2 2 eeq = en1 1 + ' KPBP L12 ' L K B N 2 N To minimize 1/f noise 1). L2 >> L 1 2 2). en1 small -----> Gain = − ' KNW1 ' K PW2 L2 L1 Allen and Holberg - CMOS Analog Circuit Design Noise in An Active Load Inverter - (Cont'd) Suppose the noise is thermal - Sec. 3.2, Eq,(13) 8kT(1+η) 3gm 8kT(1+η1) 2 eeq = 1 + 3gm1 2 en = gm2 2 (1+η2)gm1 2 gm1 (1+η1)gm2 (1+ η ) KP'W2 1/2 8kT(1+η 1) L2 2 2 eeq = 1+ 3gm1 (1+η1)KN'W1 L1 or 2 eeq = 8kT(1+η 1) 1+η2 gm2 1 + 3gm1 1+η1 gm1 To minimize thermal noise gm1 1. Maximize gain gm2 2. Increase gm1 = 2KNW1 L1 ID Page VI.1-18 Allen and Holberg - CMOS Analog Circuit Design Page VI.1-19 Noise in Other Types of Inverters Current Source Load Inverter -> same as active load inverter Push-Pull InverterVDD e2 n2 M2 vOUT vIN M1 e2 n1 VSS 1 rout = g ds1 + g ds2 2 2 2 eout = (gm1rout)2 en1 + (gm2rout)2 en2 vout = −(gm1 + gm2 )rout vin gm1 gm2 2 2 2 2 2 eeq = g en1 + g + g en2 m 2 m1 + g m 2 m1 2 eeq = 2 gm2 2 en2 1 + gm1 2 en1 2 en1 g m 2 2 1 + gm1 2 2 = To minimize noise - Reduce en1 and en2 . ' KPBP L1 2 1 + ' L2 K NBN 2 en1 ' KP W 2L 1 2 1 + K ' W L N 1 2 Allen and Holberg - CMOS Analog Circuit Design Page VI.1-20 SUMMARY OF MOS INVERTERS Inverter Type AC Voltage Gain AC Output Resistance Bandwidth (CGB=0) gm2 p-channel active load sinking inverter -gm1 gm2 1 gm2 n-channel active load sinking inverter -gm1 gm2+gmb2 1 gm2 +g mb2 Current source load sinking inverter -gm1 gds1+gds2 1 gds1+gds2 -(gm1 +gm2 ) gds1+gds2 1 gds1+gds2 Push-Pull inverter CBD1 +C GS1 +C GS2 +C BD2 gm2+gmb2 CBD1 +CGD1 +CGS2 +CBD2 gds1+gds2 CBD1 +CGD1 +CGS2 +CBD2 gds1+gds2 Equivalent, input-referred,meansquare noise voltage g v2 gm1 n1 2 +v2 n2 g v2 gm1 n1 2 +v2 n2 g v2 gm1 n1 2 +v2 n2 m2 m2 v2 gm1 n1 CBD1 +CGD1 +CGS2 +CBD2 g +g m1 m2 m2 2 v2 g + g n2 m2 m1 +g m2 2 Allen and Holberg - CMOS Analog Circuit Design Page VI.1-21 KEY MOSFET RELATIONSHIP USEFUL FOR DESIGN Assume MOSFET is in saturation. 1.) KW iD = 2L (vGS − VT ) 2 2.) vDS (sat) = 3.) gm = 2iD KW/L 2IDKW L or vGS = 2iD KW/L − VT or KW iD(sat) = 2L vDS (sat)2 or KW gm = L (VGS − V T) Allen and Holberg - CMOS Analog Circuit Design Page VI.2-1 VI.2 - DIFFERENTIAL AMPLIFIERS Definition of a Differential Amplifier v1 + Differential Amplifier v2 vOUT - v 1 + v 2 2 vOUT = AVD(v1 − v2) ± A VC (100) Differential voltage gain = AVD Common mode voltage gain = AVC (1) AVD Common mode rejection ratio = (1000) AVC VOS(out) Input offset voltage = VOS(in) = (2-10mV) AVD Common mode input range = VICMR (VSS+2V<VICMR <VDD−2V) Power supply rejection ratio Noise (PSRR) Allen and Holberg - CMOS Analog Circuit Design Page VI.2-2 VI.2-1 - CMOS DIFFERENTIAL AMPLIFIERS N-Channel Input Pair Differential Amplifier VDD M3 M4 iD3 iD1 vG1 iOUT iD4 iD2 M1 + vGS1 - vOUT M2 + - vGS2 VSS vG2 Allen and Holberg - CMOS Analog Circuit Design Page VI.2-3 P-Channel Input Pair Differential Amplifier VDD IDD + + vGS1 vG1 vGS2 - M1 iD1=iD3 M2 iD2 iOUT vOUT iD4 M3 vG2 M4 VSS Allen and Holberg - CMOS Analog Circuit Design Page VI.2-4 Large Signal Analysis of CMOS Differential Amplifiers iD1 iD2 M1 M2 + + vGS1 vGS2 - ISS (1). vID = vGS1 − v GS2 = (2). ISS = iD1 + iD2 Solving for iD1 and iD2 gives, ISS ISS + (3). iD1 = 2 2 vID 2iD1 β− - 2iD2 β 2 β 2 v ID − ISS 4ISS 2 β And Where vID < 2 2 β 2 v ID β − ISS 4ISS 2 ∂iD1 βISS gm = ∂v = 4 ID ISS ISS (4). iD2 = − vID 2 2 IS S β I ISS 1 .8 iD2 .6 .4 iD1 .2 -2 -2 2 2 vID ISS ß Allen and Holberg - CMOS Analog Circuit Design Page VI.2-5 Transconductance Characteristics of the Differential Amplifier Circuit VDD = 5V 9u/3u 9u/3u vOUT iD1 iD2 3u/3u + 50K v- 3u/3u v+ 3u/3u 3u/3u VSS = -5V Simulation Results 140uA 120uA 100uA iD1 80uA 60uA 40uA i D2 20uA 0uA -5V -3V -1V v+ 1V 3V 5V Allen and Holberg - CMOS Analog Circuit Design Page VI.2-6 Voltage Transfer Curve of n-channel Differential Amplifier VDD 9u/3u 9u/3u 50kΩ vOUT v+ 3u/3u 3u/3u v- 3u/3u 3u/3u VSS 5 v- = 0V v- = -1V v- = 1V Output Voltage 3 1 -1 v- = -1V v- = 1V -3 v- = 0V -5 -5 -3 -1 1 Positive Input Voltage 3 5 Allen and Holberg - CMOS Analog Circuit Design Page VI.2-7 Voltage Transfer Curve for a p-channel Differential Amplifier VDD 9u/3u v+ 9u/3u v- 9u/3u 9u/3u vOUT 3u/3u 3u/3u 50kΩ VSS 5 v- = 1V 3 Output Voltage v- = 0V v- = -1V 1 -1 v- = 1V -3 v- = 0V v- = -1V -5 -5 -3 -1 1 Positive Input Voltage 3 5 Allen and Holberg - CMOS Analog Circuit Design Page VI.2-8 COMMON MODE INPUT RANGE P-Channel Input Pair Differential Amplifier VDD + M5 vSD5 + vSG1 vG1 - + + vSG2 - v M1 SD1 vG2 M2 - vOUT M3 + M4 vGS3 - VSS Lowest common mode input voltage at gate of M1(M2) vG1(min) = VSS + vGS3 + vSD1 − vSG1 for saturation, the minimum value of vSD1 = vSG1 − |V T1| Therefore, vG1(min) = VSS + vGS3 − |V T1| or, vG1(min) = VSS + ISS β + VTO3 − |VT1| vG1(max) = VDD − v SD5 − v SG1 = VDD − v SD5 − 2ID1 β1 − |V T1| Allen and Holberg - CMOS Analog Circuit Design Page VI.2-9 COMMON MODE RANGE-CONT'D Example Assume that VDD varies from 8 to 12 volts and that VSS = 0. Using the values of Table 3.1-2, find the common mode range for worst case conditions. Assume that ISS = 100µA, W1/L1 = W2/L2 = 5, W3/L3 = W4/L4 = 1, and vSD5 = 0.2V. Include the worst case value of K' in the calculations. If V DD varies 10 ± 2V, then we get vG1(max) = VDD − v SD5 − = 8 − 0.2 − vG1(min) = VSS + =0+ ISS β1 − |V T1| 100 − 1.2 = 6.6 − 1.67 = 4.99V 5x7.2 ISS β3 + VTO3 − |V T1| 100 + 1.2 − 0.8 = 0.4 + 2.31 = 2.71V 1x18.7 Therefore, the input common mode range of the p-channel input differential amplifier is from 2.71V to 4.99V Allen and Holberg - CMOS Analog Circuit Design 8V 4.99V Input Common Mode Range ≈ 2.22V 2.71V 0V Page VI.2-10 Allen and Holberg - CMOS Analog Circuit Design Page VI.2-11 CMOS DIFFERENTIAL AMPLIFIER Small Signal Differential Mode Gain N-Channel input differential amplifier VDD M3 M4 vOUT M1 vG1 M2 VGG vG2 M5 VSS Exact small signal model rds1 D1=G3=D3=G4 G1 G2 +v id + + vg1 _ 1 v g2 g m3 _ rds2 g m1 v gs1 + D2=D4 gm2 v gs2 + v gs4 rds3 S1=S2 v gs1 = - v gs2 rds4 g m4 vgs4 _ S3 vout vs1 =vs2 ≈ 0 rds5 _ + ⇒v s1 ≈ vs2 ≈ 0 S4 Simplified small signal model using symmetry - D1=G3=D3=G4 D2=D4 G1 G2 +v id + + vg1 _ 1 v g2 g m3 _ + gm1 v gs1 g m2 vgs2 _ vgs1 = 0.5vid and v gs2 = −0.5vid + gm4 v gs4 vout v gs4 rds3 rds2 i'out rds1 S1=S2=S3=S4 rds4 - Allen and Holberg - CMOS Analog Circuit Design Page VI.2-12 CMOS DIFFERENTIAL AMPLIFIER Unloaded Differential Transconductance Gain (RL =0) g m1 g m4 (r ds1 || rds3 ) iout' = −gm4vgs4 − g m2vgs2 = v − gm2vgs2 1 + g m 3 (r ds1 | | r ds3 ) gs1 If gm3(r ds1 || rds3) >> 1, gm3 = gm4 , and g m1 = gm2 = gmd, then iout' ≈ g m1vgs1 − gm2vgs2 = gmd(v gs1 − vgs2) = gmdvid or i out ' ≈ g m d v id = K N'WISS vi d L Unloaded Differential Voltage Gain (RL = ∞) gmd 2 v i d = (λ + λ ) v out ≈ g ds2 + g ds4 N P K N'W v ISSL i d Example If all W/L ratios are 3µm/3µm and ISS = 10µA, then gmd(N-channel) = (17x10-6)(10x10-6) = 13 µA/V gmd (P-channel) = (8x10-6)(10x10-6) = 8.9 µA/V and vout 2(13x10-6) (N-channel) = = 86.67 vid (0.01+0.02)10x10-6 vout 2(8.9x10-6) (P-channel) = = 59.33 vid (0.01+0.02)10x10-6 Allen and Holberg - CMOS Analog Circuit Design Page VI.2-13 INTUITIVE SMALL SIGNAL ANALYSIS OF MOSFET CIRCUITS Principle: Consider only small changes superimposed on the dc conditions. Technique: Identify the transistor(s) that convert input voltage to current (these transistors are called the active devices). Trace the currents to where they flow into the resistance seen from a given node and multiply this resistance times the currents to find the voltage at this node. Example - Differential Amplifier VDD gm1vin 2 M3 gm1vin 2 M4 Rout gm1vin 2 gm2vin 2 M1 + M2 vin 2- VGG v + in - vOUT vin +2 M5 VSS Current flowing into the output node (drains of M2 and M4) is gm1vin gm2vin iout = 2 + 2 Output resistance, R out, seen at this node is 1 R out = rds2||rds4 = g +g ds2 ds4 Therefore, the open circuit voltage gain is v out gm1+gm2 gm1 gm2 vin = 2(gds2+gds4) = gds2+gds4 = gds2+gds4 Allen and Holberg - CMOS Analog Circuit Design Page VI.2-14 CMOS DIFFERENTIAL AMPLIFIER Common Mode Gain The differential amplifier that uses a current mirror load should theoretically have zero common mode gain. For example: VDD M1-M3-M4 M3 M4 vOUT vG1 M1 vG2 M2 M1-M2 VSS Total Common mode output due to v I C Common mode = output due to M1-M3-M4 path Common mode − output due to M1 −M2 path Therefore, the common mode gain will approach zero and is nonzero because of mismatches in the gain between the two paths. Allen and Holberg - CMOS Analog Circuit Design Page VI.2-15 CMOS DIFFERENTIAL AMPLIFIER Consider the following differential amplifier VDD M3 M4 vO1 vO2 vIC M1 VGG5 vIC M2 M5 VSS Use of symmetry to simplify gain calculations VDD M3 M4 vO1 vO2 vIC M1 VGG 1 xM5 2 M2 1 xM5 2 VSS vIC VGG Allen and Holberg - CMOS Analog Circuit Design Page VI.2-16 CMOS DIFFERENTIAL AMPLIFIER Small signal model gmbs1 vbs1 + rds1 + vIC=vg1 - vs1 - 2rds5 + gm1 vgs1 vo1 rds3 gm3 vo1 - gm1 +gmbs1 vs1 gm1 vg1 rds1 r ds1 + vIC=vg1 2rds5 - + vs1 - + gm1 +gmbs1 vs1 r ds3 1 gm1 +gmbs1 1 gm3 gm1 vg1 vo1 - Writing nodal equations 0.5g ds + g ds1 + g mbs1 vs1 − gds1 vo1 = gm1 vIC −g ds1 + g m1 + g m b s 1 v o1 + g ds1 + g ds3 + g m 3 vo1 = −gm1 vIC vo1 Solving for v gives, IC −0.5gm1gds5 vo1 = vIC gds3+gm30.5g ds + g m1 + g mbs1 + g ds1 + 0 .5g ds1 g ds5 or −0.5gm1gds5 −gds5 vo1 vIC ≈ gm3g m1 + g mbs1 ≈ 2gm3 Allen and Holberg - CMOS Analog Circuit Design Page VI.2-17 COMMON MODE REJECTION RATIO (CMRR) Differential mode gain Avd CMRR = Common mode gain = Avc For the previous example, |CMRR| = gm1 gm3 2(g m1 + g mbs1) 2gm1 ≈g gds5 ds5 gm1gds5 2g m3 g m1 + g mbs1 = Therefore, current sinks/sources with a larger output resistance(rds5) will increase the CMRR. Example Let all W/L ratios be unity, ISS = 100µA, and use the values of Table 3.1-2 to find the CMRR of a CMOS differential amplifier. gm1 = 2x17(µA/V2)x100µA = 58.3µS gds5 = 0.01V-1 x 100µA =1µS Therefore, |CMRR| = 116 Allen and Holberg - CMOS Analog Circuit Design Page VI.2-18 CMOS DIFFERENTIAL AMPLIFIERS Parasitic Capacitances VDD M3 M4 Cgd4 Cout vOUT CM vG1 M1 vG2 M2 CT ISS VSS CT = tail capacitor (common mode only) CM = mirror capacitor = Cdg1 + Cdb1 + Cgs3 + Cgs4 + Cdb3 COUT = output capacitor ≈ Cbd4 + Cbd2 + Cgd2 + CL Small Signal Model + + g m1vgs1 v gs1 = vgs2 = vid /2 -v id /2 - - + v gs3 rds3 + C gd4 rds2 rds1 1 g m3 - CM gm4v gs3 g m2v gs2 rds4 C OUT v out - We will examine the frequency response of the differential amplifier in more detail later. Allen and Holberg - CMOS Analog Circuit Design Page VI.2-19 SLEW RATE Slew rate is defined as an output voltage rate limit usually caused by the current necessary to charge a capacitance. dV dT i.e. i = C For the CMOS differential amplifier shown, VDD M3 M4 CL + M1 + v -O M2 vIN ISS VSS ISS Slew rate = C L where CL is the total capacitance seen from the output node to ground. If C L = 5pF and ISS = 10 µA, then the SR = 2V/µS Allen and Holberg - CMOS Analog Circuit Design Page VI.2-20 CMOS DIFFERENTIAL AMPLIFIERS NOISE Assumption: Neglect thermal noise(low frequency) and ignore the thermal noise sources of rd and rs . Therefore: 2 KF ind = iD AF (AF = 0.8 and KF = 10-28 ) fCoxL2 or 2 2 vnd = ind KF (AF-1) = 2 2WL i D gm 2fµoCox Allen and Holberg - CMOS Analog Circuit Design Page VI.2-21 VDD IDD v2 eq1 v2 eq2 M1 M2 i2 o + M3 M4 v2 eq3 v2 eq4 vOUT - VSS Allen and Holberg - CMOS Analog Circuit Design Page VI.2-22 CMOS DIFFERENTIAL AMPLIFIERS NOISE Total output noise current is found as, 2 iod 2 2 2 2 = gm1 2 v1 + g m2 2 v2 + gm32 v3 + g m4 2 v4 2 Define vneq as the equivalent input noise voltage of the differential amplifier. Therefore, 2 2 iod = gm12 vneq or gm3 2 2 2 2 2 2 vneq = veq1 + veq2 + veq3 + veq4 gm1 Where gm1 = gm2 and gm3 = gm4 VDD I DD v2 neq M1 M2 i2 o M3 + M4 - vOUT VSS It is desirable to increase the transconductance of M1 and M2 and decrease the transconductance of M3 and M4. (Empirical studies suggest p-channel devices have less noise) Allen and Holberg - CMOS Analog Circuit Design Page VI.2-23 CMOS DIFFERENTIAL AMPLIFIERS Minimization of Noise gm3 2 2 2 2 2 2 vneq = veq1 + veq2 + g veq3 + veq4 m1 In terms of voltage spectral-noise densities we get, gm3 2 2 2 2 2 2 eeq = en1 + en2 + g en3 + en4 m1 1/f noise Let KF B 2 en = = fWL 2fCoxWLK' 2 2 assume en1 = en2 ∴ and 2 2 en3 = en4 K N 'B N L12 2BP 2 eeq (1/f) = fW L 1 + K 'B L 1 1 P P 3 1) Since BN ≈ 5BP use PMOS for M1 and M2 with large area. K P'BP L1 1 2 ≈ 12.5 so that eeq (1/f) ≈ 2) Make L < K 'B 3 NN Thermal Noise 16KT(1+η1) 2 eeq (th) = 3 W1 2K P'I 1 L 1 1) Large value of gm1. L1 2) L3 < 1. K N ' W3 1 + L3 K P'W1 L1 2BP fW1L1 Page VI.3-1 Allen and Holberg - CMOS Analog Circuit Design VI.3 - CASCODE AMPLIFIERS V I.3.1-CMOS CASCODE A MPLIFIERS Objective Prevent Cgd of the inverter from loading the previous stage. Gives very high gain. Cascode Amplifier Circuit VDD VGG2 Miller effect: M3 vout VGG1 M2 Cgd1 + vin M1 v 1 VSS Large Signal Characteristics When V GG1 designed properly, vout(min) = V on1 + V on2 Inverter Cin ≈ Gain x Cgd1 Cascode Cin ≈ 3Cgd1 v1 ≈ 2 vin Page VI.3-2 Allen and Holberg - CMOS Analog Circuit Design CASCODE AMPLIFIER-CONTINUED Small Signal Model + rds2 gm2 v1 gmbs2 v1 + + vin - rds1 v1 gm1 vin vout rds3 - (gm2 +gmbs2 )v1 C1 rds2 + + C2 vin gm1vin - rds1 v1 - 1 gm2 (1+η2 ) + C3 rds3 gm2( 1+ η2 )v1 vout - Nodal Equations: (gm1 − sC1)vin + (g m2 + g mbs2 + g ds1 + g ds2 + sC1 + sC2)v1 − (gds2)vout = 0 −(gds2 + gm2 + gmbs2)v1 + (gds2 + gds3 + sC3)vout = 0 Solving for v out/vin gives (sC1-gm1)gm2(1+η) ≅2 s (C3C1+C3C2)+s(C 1+C2)(g ds2+g ds3) +C3gm2 (1+η)+gds3gm2(1+η) Page VI.3-3 Allen and Holberg - CMOS Analog Circuit Design Small Signal Characteristics Low-frequency Gains: vout − g m1 (g ds2 + g m2 + g mbs2 ) = vin g ds1 g ds2 + g ds3 (g m2 + g mbs2 + g ds1 + g ds2 ) ≈ −gm 1 gds3 = 2K'(W1/L 1)ID1 λ3ID3 Also (see next page), v1 −2gm1 = g (1 + η ) vin m2 2 Gain Enhancement: VDD VGG2 M4 M3 vout VGG1 M2 I4 I2 I1 v in M1 vout − gm1 vin ≈ gds3 2K'W1 I1 vout L1 vin ≈ λ I2 But I1 = I2 + I4 VSS I4 = 24I2 ⇒ x5 Gain enhancement Page VI.3-4 Allen and Holberg - CMOS Analog Circuit Design Voltage Gain of M1: v1 −gm1 =g ? vin m2 What is the small signal resistance looking into the source of M2? Consider the model below: i1 gm2 vgs2 + v1 = vs2 r ds2 r ds3 - vs2 = (i1 + gm2vgs2)r ds2 + i1rds3 = rds2i1 + gm2(−vs2)r ds2 + i1rds3 or vs2(1 + g m2 rds2) = i1(rds2 + rds3) Therefore, r ds2 + r ds3 r ds2 + r d s 3 r d s 3 vs2 1 ≈gr = g 1 + r R= i =1 + g r 1 m2 d s 2 m2 ds2 m2 ds2 Some limiting cases: 1 rds3 = 0 ⇒ R = g m2 2 rds3 = rds2 ⇒ R = g m2 and rds3 >> rds2 ⇒ R = g rds3 m2 rds2 Therefore, the gain vin to v1 is − g m1 (g ds2 + g ds3 ) −2gm1 −2gm1 v1 vin ≈ (g m2 + g mbs2 )g ds3 ≈ g m2 + g mbs2 ≈ gm2 Page VI.3-5 Allen and Holberg - CMOS Analog Circuit Design CASCODE AMPLIFIER-CONTINUED High Resistance Driver for the Inverter M1-M2 VDD M2 M4 VGG2 Cgd1 ro = g 1 ds3 +gds4 vout iin + M1 v1 M3 CΜ VSS C2 iin R1 C1 R1 = (gds3 + g ds4 )-1 + v1 - + gmv1 C3 R3 vout - R3 = (gds1 + g ds2 )-1 C1= Cgs1 + Cbd3 + Cbd4 + Cgd3 + Cgd4 C2 = Cgd1 vout(s) = iin(s) C3 = Cbd1 + Cbd2 + Cgd2 + CL −gm1 gm1 1−s G1G3 C2 1+R (C +C )+R (C +C )+g R R C s+(C C +C C +C C )R R s2 12 13 23 13 1 1 3 3 2 3 m1 1 3 2 Page VI.3-6 Allen and Holberg - CMOS Analog Circuit Design Note: s s 1 s2 1 d(s) = 1 + as + bs2 = 1 − 1 − = 1 − s + + p p 1 p2 p2 p1p2 1 If |p2| >> |p 1| , then s s2 d(s) ≈ 1 − p + p p 1 12 or 1 p1 = − a and a p2 = − b Using this technique we get, p1 ≈ −1 −1 ≈g R R C R1(C1+C3)+R3(C2+C3)+gm1R1R3C2 m1 1 3 2 (Miller effect on C2 causes p1 to be dominant; CM ≈ gm1R2Cgd1) −gm1C2 p2 ≈ C C +C C +C C 12 13 23 Page VI.3-7 Allen and Holberg - CMOS Analog Circuit Design CASCODE AMPLIFIER - CONTINUED How does the Cascode Amplifier solve this problem? VDD M5 VGG5 M2 vout VGG2 M4 1 ro = g + g ds3 ds4 Cgd1 iin M1 M3 VSS Cgd1 iin r1 + v1 - rds2 C2 gmv1 + v2 r2 - gm2(1+η)v2 + C3 r3 r1 = ro = (gds3 + gds4)-1 C2 = Cgs2 + Csb2 + Cdb1 + Cgd1 r 2 = g ds1 + g m 2 (1 + η ) -1 1 ≈g m2 C3 = Cgd2 + Cdb2 + Cgd5 + Cdb5 + CL gm2 -1 1 r3 ≈ g + g d s 5 ≈ g ds5 ds1 g ds2 vout - Page VI.3-8 Allen and Holberg - CMOS Analog Circuit Design Cascode amplifier with higher gain and output resistance VDD io VGG4 M4 VGG3 M3 VGG2 gm2 v1 Vout r ds2 gmbs2 v1 G1 M2 Vin - g m3 v4 gmbs3 v4 r ds3 vout D1=S2 + + vin M1 VSS + D2 gm1 v in v1 - r ds1 r ds4 + v4 - ' =rds3 - Allen and Holberg - CMOS Analog Circuit Design Page VI.4-1 VI.4 - OUTPUT AMPLIFIERS Requirements 1. Provide sufficient output power in the form of voltage or current. 2. Avoid signal distortion for large signal swings. 3. Be efficient. 4. Provide protection from abnormal conditions. Types of Output Stages 1. Class A amplifier. 2. Source follower. 3. Push-Pull amplifier ( inverting and follower). 4. Substrate BJT. 5. Negative feedback (OP amp and resistive). Page VI.4-2 Allen and Holberg - CMOS Analog Circuit Design CLASS A AMPLIFIER VDD VGG2 M2 IQ Vin Iout M1 Vout CL RL VSS KnW1 2 Iout 2L1 (VDD − VSS − VT1) − IQ KpW2 -= 2 + Iout 2L2 (VDD − V GG2 − |VT2|) < Iout += |Iout| determined by: dvout dt = CL (slew rate) vout(peak) 2. |I out| = RL 1. |Iout| = C L Vout(peak) 2 Efficiency = Psupply = (V DD + V SS ) PRL 1 1 = 2λI rout = g ds1 + g ds2 D ≤ 25% (typically large) Page VI.4-3 Allen and Holberg - CMOS Analog Circuit Design SOURCE FOLLOWER N-Channel Push Pull VDD vIN VDD M1 M1 vOUT VGG vIN M2 VSS Large Signal Characteristics vOUT = vIN − vGS1 Maximum Output Swing Limits vOUT (MAX) = VDD − VT1 (VT1 greater than V T0 because of v BS) Single Channel Follower: vOUT(MIN) = V SS Push Pull Follower: vOUT(MIN) = VSS + |VT2| (VT2 greater than VT0 because of v BS) vOUT M2 VSS Page VI.4-4 Allen and Holberg - CMOS Analog Circuit Design SOURCE FOLLOWERS Small Signal Characteristics Single Channel Follower (Current source and active load): C1 + + gm1 vin vin gm1 vout - rds1 gmbs1 vout rds2 C2 gm2 vgs2 vout - Small Signal Voltage Transfer Function: gm1 vout = g +g +g +g w here g m2 = 0 i f v GS2 = V G G vin ds1 ds2 m1 mbs1+gm2 Example: W 10 µ m If VDD= −VSS =5V, vOUT = 0V, iD = 100µA, and L =10 µ m , then; vout 41.23 = 1+1+41.23(1+0.2723)+41.23 = 0.4309 when vGS2 = vOUT vin vout 41.23 = 1+1+41.23(1+0.2723) = 0.751 when vGS2 = VGG vin vout ≈ 0.786 (gds1= gds2 ≈ 0) Approximation gives v in Output Resistance: 1 r out = gds1+gds2+gm1+gmbs1+gm2 w here g m2 = 0 i f v GS2 = V G G rout = 10.5 KΩ (vGS2 = vOUT) and rout = 18.4 KΩ (vGS2 = VGG) Page VI.4-5 Allen and Holberg - CMOS Analog Circuit Design SOURCE FOLLOWERS Push Pull Source Follower Model: C1 M1 + gm1vin vin gm1vout M2 + gm2 vin gm2vout rds1 1 gmbs1 rds2 1 gmbs2 C2 v out - - Small Signal Voltage Transfer Function: g m1 + g m 2 vout vin = g ds1 + g ds2 + g m1 + g mbs1 + g m2 + g m b s 2 Example: W 10 µm If VDD = −VSS = 5V, vOUT = 0V, iD = 100µA, and L = 10µm then, vout 4 1.23 + 28.28 = 1 + 0.5 + 41.23(1 + 0.2723) + 28.28(1 + 0.1268) = 0.81 vin Output Resistance: 1 r out = g ds1 + g ds2 + g m 1 + g mbs1 + g m 2 + g m b s 2 = 1 1.7K Ω Page VI.4-6 Allen and Holberg - CMOS Analog Circuit Design PUSH-PULL INVERTERING CMOS AMPLIFIER ConceptVDD VTR2 vIN VTR1 M2 + Iout + - Vout M1 CL RL VSS ImplementationVDD M5 M6 M1 M3 VGG3 M2 M4 Iout VGG4 Vout vIN M7 VSS CL M8 RL Page VI.4-7 Allen and Holberg - CMOS Analog Circuit Design PUSH-PULL SOURCE FOLLOWER VDD M2 Iout VTR Vout vIN CL M1 RL VSS VDD VGG6 M6 M2 M5 Iout Vout M4 M1 vIN M3 VSS CL RL Page VI.4-8 Allen and Holberg - CMOS Analog Circuit Design USE OF NEGATIVE FEEDBACK TO REDUCE ROUT VDD error amplifier M2 - + Iout Vout vIN - + CL M1 RL VSS Use of negative feedback to reduce the output resistance of Fig. 6.3-4. VDD M2 R1 vIN R2 Iout M1 Vout CL RL VSS Use of resistive feedback to decrease the output resistance of Fig.6.3-4. Allen and Holberg - CMOS Analog Circuit Design VI.5 - SUMMARY • Analog Amplifier Building Blocks Inverters - Class A Push-Pull - Class AB or B Cascode - Increased bandwidth Differential - Common mode rejection, good input stage Output - Low output resistance with minimum distortion Page VI.5-1 Allen and Holberg - CMOS Analog Circuit Design SECTION 7 - COMPARATORS Page VII.0-1 Allen and Holberg - CMOS Analog Circuit Design Page VII.0-1 VII. COMPARATORS Contents VI.1 VI.2 VI.3 VI.4 VI.5 Comparators Models and Performance Development of a CMOS Comparator Design of a Two-Stage CMOS Comparator Other Types of Comparators Improvement in Comparator Performance A. Hysteresis B. Autozeroing VI.6 High Speed Comparators Organization Chapter 10 D/A and A/D Converters Chapter 11 Analog Systems SYSTEMS Chapter 7 CMOS Comparators Chapter 8 Simple CMOS OTA's Chapter 9 High Performance OTA's COMPLEX CIRCUITS Chapter 5 CMOS Subcircuits Chapter 6 CMOS Amplifiers SIMPLE Chapter 2 CMOS Technology DEVICES Chapter 3 CMOS Device Modeling Chapter 4 Device Characterization Allen and Holberg - CMOS Analog Circuit Design Page VII.1-1 VII.1 - CHARACTERIZATION OF COMPARATORS What is a Comparator? A comparator is a circuit which compares two analog signals and outputs a binary signal based on the comparsion. (It can be an op amp without frequency compensation.) Characterization of Comparators We shall characterize the comparator by the following aspects: • Resolving capability • Speed or propagation time delay • Maximum signal swing limits • Input offset voltage • Other Considerations Noise Power Etc. Allen and Holberg - CMOS Analog Circuit Design Page VII.1-2 VOLTAGE COMPARATORS Definition of a Comparator VA VB + VOUT - Noninverting VOUT VOH VOUT = V OH V OL when VA ≥ VB VA - VB w hen V A < V B VOL Inverting VOUT VOUT = V OL V OH when VA ≥ VB VOH w hen V A ≤ V B VA - VB VOL Allen and Holberg - CMOS Analog Circuit Design Page VII.1-3 COMPARATOR PERFORMANCE 1. Speed or propagation time delay. The amount of time between the time when VA - V B = 0 and the output is 50% between initial and final value. 2. Resolving capability. The input change necessary to cause the output to make a transition between its two stable states. 3. Input common mode range. The input voltage range over which the comparator can detect V A = VB . 4. Output voltage swing (typically binary). 5. Input offset voltage. The value of V OUT reflected back to the input when VA is physically connected to V B. Allen and Holberg - CMOS Analog Circuit Design Page VII.1-4 APPROACHES TO THE DESIGN OF VOLTAGE COMPARATORS Open Loop Use of a high-gain differential amplifier. V OH - V O L Gain = resolution of the comparator Regenerative Use of positive feedback to detect small differences between two voltages, VA and VB. I.e., sense amplifiers in digital memories. Open Loop - Regenerative Use of low gain, high speed comparator cascaded with a latch. Results in comparators with very low propagation time delay. Charge Balancing Differential charging of a capacitor. Compatible with switched capacitor circuit techniques. Type Offset Voltage (Power supply) Resolution Speed (8 bit) Open-loop 1-10 mV 300µV (±5V) 10 MHz Regenerative Charge Balancing 0.1 mV 50µV (±5V) 50 MHz 0.1 mV 5mV (5V) 30 MHz Allen and Holberg - CMOS Analog Circuit Design Page VII.1-5 COMPARATOR MODELS - OPEN LOOP Zero Order Model VOUT VOH + - VP - VN VOL Model VP + + + fo VP - VN - - VN fo( V P V OH - VN ) = V OL VO f or ( V P - V N ) ≥ 0 for ( V P - V N ) ≤ 0 Allen and Holberg - CMOS Analog Circuit Design Page VII.1-6 COMPARATOR MODELS - CONT'D First Order Model Transfer Curve VOUT VOH VIL VP - VN VIH VOL Model VP + + + f1 VP - VN VN VO - V O H f or ( V P - V N ) ≥ VIH A V - V f o r V ≤ V - V ≤ V N) IL (P N) IH f1( V P - V N ) = V( P V OL for ( V P - V N ) ≤ VIL Allen and Holberg - CMOS Analog Circuit Design Page VII.1-7 COMPARATOR MODELS - CONT'D First Order Model with Offset Transfer Curve VOUT VOH VOS VIL VP - VN VIH VOL First Order Model with Offset +VOS VP + - V'P + + + f1 V'P - V'N - - - V'N VN Time Response of Noninverting, first order model VOH v = VOH + VOL 2 VOUT VOL VIH VP - VN VO v = VIH + VIL 2 tP VIL Time Allen and Holberg - CMOS Analog Circuit Design Page VII.2-1 VII.2 - DEVELOPMENT OF A CMOS COMPARATOR SIMPLE INVERTING COMPARATOR VDD vN M2 I2 IB M1 VBIAS vO VSS Fig. 7.2-1 Simple inverting comparator ∆VIN VDD vO vN VTRP Fig. 7.2-2 DC transfer curve of a simple comparator Low gain ⇒ Poor resolution VTRP = f V D D + process parameters Allen and Holberg - CMOS Analog Circuit Design Page VII.2-2 CALCULATION OF THE TRIP POINT, VTRP vO t. VDD VDD vO = V IN + VT2 c 2a M t. a 2s M VIN M2 vO VBIAS M1 M1 sat. M1 act. VBIAS - VT1 VSS Operating RegionsvDS1 ≥ v GS1 - VT VSS VSS VIN vN VTRP VDD ‘ vO - VSS ≥ V BIAS - VSS - VT1 v O ≥ V BIAS - V T 1 vSD2 ≥ vSG2 - VT2 ‘ V DD - vO ≥ VDD - vIN - VT2 v O ≤ v I N + VT2 Trip PointAssume both M1 and M2 are saturated, solve and equate drain currents for VTRP. Assume λ ≈ 0. K N W1 2 iD1 = 2 L V BIAS - V SS - V T 1 1 K P W2 2 iD2 = 2 L V D D - v I N - VT2 2 iD1=iD2 ‘ vIN = VTRP = VDD- VT2 - KN( W1/L1) KP( W2/L2) ( V BIAS - V SS - V T 1) W1 W2 I.e. V DD = -VSS = 5V, VBIAS = -2V and KN L = KP L 1 2 VTRP = 5-1-(-2+5-1) = 4-2 = 2V Allen and Holberg - CMOS Analog Circuit Design Page VII.2-3 COMPARATOR USING A DIFFERENTIAL AMPLIFIER VDD M3 M4 vO M1 vP M2 VBIAS vN M5 vO VOH = VDD VOH' M1 & M2 in saturation VOL' VOL VSS -1 +1 Gain is still low for a comparator vP - vN Av Allen and Holberg - CMOS Analog Circuit Design Page VII.2-4 DERIVATION OF OUTPUT SWING LIMITS VDD vP > vN M3 I1 vP M4 I2 M1 M2 vO vN 1. Current in M1 increases and current in M2 decreases. 2. Mirroring of M3-M4 will cause vO to approach VDD . 3. VOH' = VDD - VDS4(sat) VOH ' = VDD - VBIAS I4 β4 VOH ' = VDD - ISS I5 Kp'( W4/L4) M5 VSS vP < vN V O H ' = VD D - I5 Kp'( W3/L3) Assume vN is a fixed DC voltage 1. vO starts to decrease, M3-M4 mirror is valid so that I1 = I2 = ISS/2 . 2. VOL ' = vN - VGS2 + VDS2 when M2 becomes non-sat. we have VDS2(sat) = VGS2 - VT so that 4. Finally, vO ‘ V DD causing the mirror M3-M4 to no longer be valid and V OH ≈ V DD. ( I 2 = I4 = 0 , I 3 = I1 = I5 ) V OL ' = v N - V T 2 3. For further decrease in vO, M2 is nonsat and therefore the VGS2 can increase allowing the sources of M1 and M2 to fall(as v P falls). 4. Eventually M5 becomes non-sat and I5 starts to decrease to zero. M2 becomes a switch and v O tracks V S2(VDS5) all the way to VSS. ∴ V OL = V SS . I 1 still equals I2 due to mirror Allen and Holberg - CMOS Analog Circuit Design Page VII.2-5 TWO-STAGE COMPARATOR Combine the differential amplifier stage with the inverter stage. • Sufficient gain. • Good signal swing. VDD M3 M4 M6 vN M1 M2 I8 M8 M5 VSS vP vO M7 Allen and Holberg - CMOS Analog Circuit Design Page VI.3-1 VII.3 - DESIGN OF A TWO-STAGE CMOS COMPARATOR DC BALANCE CONDITIONS FOR TWO-STAGE COMPARATOR • Try to keep all devices in saturation - more gain and wider signal swings. • Based on gate-source and DC current relationship. I.e. if M1 and M2 are two matched devices and if VGS1 = VGS2, then ID1 = I D2 or vice versa. W1 Let S1 = L , 1 M1 and M2 matched gives S 1 = S2. M3 and M4 matched gives S 3 = S4. also, I 1 = I2 = 0.5I5. From gate-source matching, we have S7 S6 VGS5 = VGS7 ‘ I7 = I5 and I 6 = I4 ← Assume S5 S4 VGS4 =VGS6 For balance conditions, I6 must be equal to I7, thus I 5 S7 S6 . I4 S5 = S4 Since I5 I4 = 2, then DC balance is achieved under the following: S6 S7 = 2 . S ‘ VDG4 = 0 ‘ M4 is saturated. S4 5 Allen and Holberg - CMOS Analog Circuit Design Page VI.3-2 SYSTEMATIC OFFSET ERROR VDD =10V + KN = 24.75 µA/V2 KP = 10.125 µA/V2 VTN = -VTP = 1V λN = 0.015V -1 λP = 0.020V -1 + 2V 20 2V 10 M3 - M6 40 M4 20 10 I8 20 10 vN M1 Find VOS to make i6 = i 7 vP M5 VSS =0V (2) Find how much vGS6 must be reduced to make i6 = i 7 ∆vGS6 = vGS6(2.115i4) - vGS6(2.057i4) 2L6 KPW6 i 4 2.115 - 2.057 = 14.11 mV (3) Reflecting ∆vGS6 into the input KN( W2/L2) 2 = 89.9 I5 λ 2 + λ 4 ∆vGS6 1 4.1 mV = 0.157 mV ∴ VOS = A (diff) = 89.9 v A v(diff) = vO =5V + 10 10 3V M7 (1) Find the mismatch between i6 and i 7 i7 1 + λ N v D S 7 W7/L7 1 + ( 0.015)(5) i5 = 1 + λ N v D S 5 W5/L5 = 1 + (0.015)(3) (1) = 1.029 i6 1 + λ P v D S 6 W6/L6 1 + ( 0.02)(5) i4 = 1 + λ P v D S 4 W4/L4 = 1 + (0.02)(2) (2) = 2.115 i5 = 2i4 ∴ i7 = (1.029)(2)i4 = 2.057i4 and i6 = 2.115i4 ∆vGS6 = i6 i7 M2 20µA M8 10 20 10 10 10 Allen and Holberg - CMOS Analog Circuit Design Page VI.3-3 DESIGNING FOR COMMON MODE INPUT RANGE VDD + VSG3 M3 I5/2 + VG1 vG1 (min) = VSS + VDS5 + VGS1 VDG1 - + M1 VGS1 - v G1 (min) = V SS + V DS5 + V T1 (max) + + VDS1 - vG1 (max) = VDD - VSG3 - VDG1(sat) + I5 VBIAS v G1 (max) = V D D - VDS5 VSS I5 2β1 M5 I5 2β3 - VT3(max) + V T1 (min) where V DG1(sat) = -VT1 - Example Design M1 through M4 for a CM input range 1.5 to 9 Volts when VDD = 10 V, ISS = 40µA, and VSS = 0V. Table 3.1-2 parameters with |VTN,P| = 0.4 to 1.0 Volts, I5 vG1(min) = VSS + VDS5 + β1 + VT1(max) 40µA + 1 (assumed VDS5 ≈ 0.1V- it probably more 1.5 = 0 + 0.1 + β1 reasonable to assume β1 is already defined and find β5) β1 = KNW 1 2 L1 = 250 µA/V ‘ vG1(max) = VDD β3 = W1 W 2 L1 = L2 = 14.70 I5 β3 - |VT3(max)| + VT1(min) K PW 3 2 L3 = 250 µA/V ‘ W3 W 4 L3 = L4 = 31.25 Allen and Holberg - CMOS Analog Circuit Design Page VI.3-4 GAIN OF THE TWO-STAGE COMPARATOR + + gm1vid r ds2 r ds4 v1 gm6v1 - r ds6 r ds7 - vid = vP - vN gm1 ds2 + g ds4 Av = g 2 Av = gm6 g ds6 + g ds7 W1 W6 KNKP L L 1 6 ( λ2 + λ4) ( λ6 + λ7) vout I1I6 W6 W1 Using L = 5, L = 5, λN = 0.015V-1 , λP = 0.02V-1 1 6 and Table 3.1-2 values; 2 (17)(8)(5)(5) . -6 95199.10-6 Av = 10 = (0.015+0.02)2 I1I6 I1I6 Assume I1 = 10 µA and I6 = 100 µA Av = 3010 V OH - VOL = Resolution = 5 mV (assume) Av 5. then VOH - V OL = 1000 3000 = 15 Volts Allen and Holberg - CMOS Analog Circuit Design Page VI.3-5 PROPAGATION DELAY OF THE TWO-STAGE COMPARATOR VDD signal swing less than the M4 output M3 vN VGS6 + - M1 M2 vP CL1 VBIAS M6 i6 key node vO i7 CL2 M5 M7 i5 VSS V GS6 = VDD - v P + V D G 2 dv iC = C dt , ∆t = ∆v CI ∆t2+ = C L2 K P W6 V 2 L6 ( D D ∆ t+ 2 VTRP3 VDD VSS VTRP3 V TRP3 - V S S - v P - V D G 2 - | V T6 | ) 2 - V DD - V TRP3 ∆t2- = CL2 W L 7 5 i L7 W5 5 ∆ t2 Slew rate = isource/sink CLi I7 Allen and Holberg - CMOS Analog Circuit Design Page VI.3-6 CALCULATION OF COMPARATOR PROPAGATION DELAY Find the total propagation delay of the comparator shown when the input vP goes from -1 to +1 in 2ns. Assume the trip point of the output(next stage) is zero. Total delay = 1st stage + 2nd stage delay delay +5V 10 10 M3 40 10 C L1=0.3pF M4 vDO vN M1 M2 20 10 vP VTRP2 = VDD - VGS6, VGS6 = |VT6 | + CL2= 10pF I7 =40µA I5=20µA ∆ t = ∆ t 1 + ∆t2 ( v DO (t 0 ) - V TRP2) ∆t1 = CL1 , I5 vDO(t0) = 5 because vP = -1V M6 I6 -5V 2I7 KP'( W6/L6) 2.40 = 2.58 V ‘ VTRP2 = 5 - 2.58 = 2.42 V 8.4 0.3pF = 38.7ns ∴ ∆t1 = (5 - 2.42) 20µA CL2 CL2 ∆t2 = v O (t 0 ) - 0 =5 I 6 - I 7 I 6 - I 7 KP6' W6 I6 = 2 L V D D - V D O (min) - VT6 2 6 [VDO(min) is an optimistic assumption based on vDS2 ≈ 0] VGS6 = 1 + VDO(min) ≈ vDS2(≈0) - vGS1 + vN = -VT1 - I5 = -1.77 KN.2 8.10-6 2 2 (4)(5 - (-1.77) -1) = 533 µA 1 0 pF ∴ ∆t2 = 5 (533 - 40) µ A = 101 ns I6 = ∆t = ∆t1 + ∆t2 ≈ 139 ns Second order consideration: Charging of Csb of M1 and M2 vO Allen and Holberg - CMOS Analog Circuit Design Page VI.3-7 SIMULATION OF THE PROPAGATION DELAY 5v +5V 10 10 M3 M4 (6) vN M1 3v 2.42v M8 20 10 M2 M6 CL1 40 10 (9) vP vO CL2 10 10 M7 -5V 1v V(9) vP 0v 20 10 tprop=167 ns Actual -1 v V(6) -1.54v COMPARATOR PROPAGATION DELAY VDD 10 0 DC 5V VSS 11 0 DC -5V VN 1 0 DC 0V VP 2 0 PULSE(-1 1 0N 1N 1N 500N 1U) M1 3 1 5 5 MNMOS W=20U L=10U M2 6 2 5 5 MNMOS W=20U L=10U M3 3 3 10 10 MPMOS W=10U L=10U M4 6 3 10 10 MPMOS W=10U L=10U M5 5 8 11 11 MNMOS W=10U L=10U M6 9 6 10 10 MPMOS W=40U L=10U M7 9 8 11 11 MNMOS W=20U L=10U M8 8 8 11 11 MNMOS W=10U L=10U CL1 6 0 0.3PF CL2 9 0 10PF IS 0 8 DC 20UA .MODEL MNMOS NMOS VTO=1 KP=17U +LAMBDA=0.015 GAMMA=0.8 PHI=0.6 .MODEL MPMOS PMOS VTO=-1 KP=8U +LAMBDA=0.02 GAMMA=0.4 PHI=0.6 .TRAN 2N 300N .PRINT TRAN V(6) V(9) V(2) .PROBE .END Approx. -3 v -5 v 0ns 50ns 100ns 150ns Time 200ns 250ns 300ns Allen and Holberg - CMOS Analog Circuit Design Page VI.3-8 SMALL SIGNAL PERFORMANCE + vin - + gm1 - gm2 R1 C1 + R2 C2 vout - vout(s) A oω p1ω p2 = s+ω vin(s) ( p 1) ( s + ω p 2) 1 ω p1 = R C 11 1 ω p2 = R2C2 Ao = gm1gm2R1R2 Example - (Fig 7.3-4) 1 1 = 10µA = 3.33M Ω ds2 + g ds4 1 ω p1 = (0.3pF)(3.33MΩ) = 1Mrps I5 = 20µA ‘ R1 = g 1 1 = 40µA(.03) = 833KΩ ds6 + g ds7 1 ω p2 = (10pF)(833KΩ) = 120Krps I7 = 40µA ‘ R2 = g g m1 = 26 µs, gm2 = 50.6µs ‘ A o = 1 099 Allen and Holberg - CMOS Analog Circuit Design Page VI.3-9 TWO-STAGE, CMOS COMPARATOR General Schematic VDD M3 M4 M6 M1 vN M2 I8 M5 M8 vP vO M7 VSS Key Relationships for Design: β iD = (vG S - VT )2 2 or v DS (sat) = Also, gm = where KW β= L 2 β ID 2iD(sat) β β ⇒ iD (sat) = 2 [vDS(sat)]2 Allen and Holberg - CMOS Analog Circuit Design Page VI.3-10 COMPARATOR DESIGN PROCEDURE 1. Set the output current to meet the slew rate requirements. dV i = C dt 2. Determine the minimum sizes for M6 and M7 for the proper ouput voltage swing. vDS (sat) = 2ID β 3. Knowing the second stage current and minimum device size for M6, calculate the second stage gain. A2 = -g m6 g ds6 + g ds7 4. Calculate the required first stage gain from A2 and gain specifications. 5. Determine the current in the first stage based upon proper mirroring and minimum values for M6 and M7. Verify that Pdiss is met. 6. Calculate the device size of M1 from A1 and I DS1. A1 = g -g m1 ds1 + g ds3 and gm1 = 2K'W/L IDS1 7. Design minimum device size for M5 based on negative CMR requirement using the following (IDS1 = 0.5IDS5): vG1(min) = VSS + VDS5 + where VDS5 = IDS5 β1 + VT1(max) 2IDS5 β5 = VDS5(sat) 8. Increase either M5 or M7 for proper mirroring. 9. Design M4 for proper positive CMR using: vG1(max) = VDD - IDS5 β3 - VTO3 (max) + VT1 10. Increase M3 or M6 for proper mirroring. 11. Simulate circuit. Allen and Holberg - CMOS Analog Circuit Design Page VI.3-11 DESIGN OF A TWO-STAGE COMPARATOR Specifications: Lambda = 0.05V-1 (L = 5 µm) Avo > 66 dB Pdiss < 10 mW VDD = 10 V CL = 2 pF VSS = 0 V tprop < 1 µs K'W Recall that β = L CMR = 4-6 V Output swing is VDD - 2V and VSS + 2V 1). For t prop << 1 µs choose slew rate at 100 V/µs dvOUT . -12 . -6 dt = ( 2 10 ) ( 100 10 ) = 200 µA ∴ I7 = CL 2). Size M6 and M7 to get proper output swing, M7: 2V > vDS7(sat) = 2I7 β7 = W7 2(200µA) → L > 5 .88 17.0µA/V 2( W7/L7) 7 M6: 2V > vDS6(sat) = 2( IOUT+I7) = β6 -g m6 -1 = 3). A 2 = g ds6 + g ds7 λ N + λ P W6 2(400µA) → L > 1 2.5 8.0 µA/V 2( W6/L6) 6 2KP'W6 I6L6 ≈ -10 4). A vo = A 1A2 = 66 dB ≈ 2000 → A1 = 200 Allen and Holberg - CMOS Analog Circuit Design Page VI.3-12 COMPARATOR DESIGN - CONT'D S4 5). Assuming vGS4 = v GS6, then I4 = S6 I6 1 choose S 4 = 1 which gives I4 = 12.5 (200µA) = 16.0 µA S5 2 00 µ A Assume S5 = 1 which gives I 5 = I 7 = 5.88 = 34 µA S7 1 and I4 = I5 = 17 µA 2 W to keep L ratios greater than 1. Choose I 4 = 1 7 µ A W4 W 6 17 ∴ I5 = 34 µA L4 = L6 200 = 1.06 ≈ 1.0 Pdiss = 10( I 7 + I 5 ) = 2.34 mW < 10 mW 1 6). A1 = λ + λ 1 4 W1 ∴ L = 200 1 2KN'W1 W1 I4 → L = [ ( λ 1 + λ 4 )A 1 ] 2 = 200 I4L 1 2KN' 1 (Good for noise) 7). V DS5 = vG1(min) - VSS V DS5 = 4 - 0 VDS5 = 8). S5 = 2I5 β5 = I5 β1 - VT1(max) (34) -1 = 2.90 V 2(17.0)(200) W5 2(34µ) → L > 0.48 (17µ)S5 5 I5 W5 34 S 7 = 200 (5.88) = 1.0 → L = 1 . 0 I7 5 Allen and Holberg - CMOS Analog Circuit Design Page VI.3-13 COMPARATOR DESIGN - CONT'D 9). VG1(max) = VDD β3 = I5 β3 - VTO3 (max) + VT1(min) I5 V D D - V G1 (max) - VTO3 (max) + V T1 (min) 2 34 µA = 2.76.10 -6 ( 1 0 - 6 - 1 + 0 . 5) 2 W3 (2.76)(2) W3 W 4 ∴L = = 0.69 L = L > 0.69 8 3 3 4 W4 (Previously showed L > 1.06 so no modification is necessary) 4 = 10). Summary W Wdrawn = (L - 1.6) L Actual Values with 5µm W1 L1 W3 L3 W5 L5 W6 L6 W7 L7 W2 = L = 200 2 W4 = L = 1.0 4 = 1.0 = 12.5 = 5.88 W1 L1 W3 L3 W5 L5 W6 L6 W7 L7 Proper Mirroring minimum geometry Design Ratios and LD = 0.8µm W 2 1000 =L = 5 2 W4 5 = L =5 4 = 1.0 62.5 =5 30 =5 (Need to adjust for proper mirroring) ⇒ 680 5 3.4 5 ‘5 5 3.4 5 ‘5 5 60 5 30 5 ↑ S6 S7 =2 S S4 5 Allen and Holberg - CMOS Analog Circuit Design Page VII.4-1 VII.4 - OTHER TYPES OF COMPARATORS FOLDED CASCODE CMOS COMPARATOR Circuit Diagram VDD MP3 MP4 MP12 MP13 MP8 MP6 MN25 MN1 MN2 vOUT MN10 MN11 MN9 MN5 v1 v2 MN24 MN7 V SS Small Signal Model 1 gm12 gm1 v2 i1 1 gm13 + i2 i2 gm2 v1 i1 rout vout - where R out ≈ (rds5gm11rds11)||((rds4||rds2)gm13rds13) = =g 1 ds5gds11 (gds2+gds4)gds13 gm11 + gm13 The small signal voltage gain is vout = r out (i2-i1) = (gm2 +gm1 )Rout vin = g where vin = v1 - v2. gm1 +gm2 vin ds5gds11 (gds2+gds4)gds13 gm11 + gm13 Allen and Holberg - CMOS Analog Circuit Design Page VII.4-2 FOLDED CASCODE CMOS COMPARATOR - CONTINUED Frequency Response Small signal modelC1 i1 1 gm1 v2 gm12 gm2 v1 + i2 C2 1 gm13 C3 i2 i1 rout vout - where C1 = C GS12 + C BS12 + C DG3 + C BD3 C2 = C GS13 + C BS13 + C DG4 + C BD4 and C3 = CDG11 + CBD11 + CDG13 + CBD13 + CLoad AVD0ω3 AVD(s) ≈ s + ω 3 where 1 ω3 = routC3 Typical performanceW 1 W 2 W 11 W 13 ID1 = ID2 = 50µA and ID3= I D4 = 100µA, L1 = L2 = L11 = L13 =1, assume C 3 ≈ 0.5pF, and using the values of Table 3.1-2 gives: gm1 = gm2 = gm11 =41.2 µS gds5 = gds11 = 0.5µS gm13 = 28.3µS gds4 = gds13 = 0.25µS Therefore, rout = 121MΩ, ω3 = 16.553krps, and AVD0 = 4,978 resulting in a gain-bandwidth of 13.11MHz. C 3∆V 0.5pFx10V Delay = ∆T = I = 100µA = 50nS max Allen and Holberg - CMOS Analog Circuit Design Page VII.4-3 OPEN LOOP COMPARATOR - MC 14575 BIAS M1 M6 M8 M10 vO - M2 + M3 M9 M11 M7 M4 M5 Performance (ISET = 50 µA) Rise time = 100 ns into 50 pF Fall time Propagation delay = 1 µs Slew rate = 2.7 Volts/µs Loop Gain = 32,000 Comments The inverter pair of M8-M9 and M10-M11 are for the purpose of providing an output drive capability and minimizing the propagation delay. Allen and Holberg - CMOS Analog Circuit Design Page VII.4-4 CLAMPED CMOS VOLTAGE COMPARATOR V DD V DD M6 M8 BIAS VPB M1 vO - + M3 M2 M9 M4 VNB M5 M7 V SS Drain of M2 and M3 clamped to the gate voltages of M4 and M5. M6 and M7 provide a current, push-pull output drive capability similiar to the current , push-pull CMOS OP amp. Comparator is really a voltage comparator with a current output. Allen and Holberg - CMOS Analog Circuit Design Page VII.6-1 VII.5 - COMPARATORS WITH HYSTERESIS HYSTERESIS Why Hysteresis? Eliminates "chattering" when the input is noisy. Comparator with no Hysteresis vin Comparator threshold Time Comparator output Comparator with Hysteresis vin vout VTRP+ VTRPTime vin VTRP- VTRP+ comparator output Allen and Holberg - CMOS Analog Circuit Design Page VII.6-2 VOLTAGE COMPARATORS USING EXTERNAL FEEDBACK Inverting vOUT VOH - vB vA vOUT + VREFR2 R1 +R2 VOHR1 R1 +R2 R2 R1 + V - REF VOL vB VOLR1 R1 +R2 Noninverting vOUT R2 vIN VOH R1 vA + vB - VREF R1 +R2 R2 vOUT vIN + - VREF R1 V R2 OL VOL R1 V R2 OH Allen and Holberg - CMOS Analog Circuit Design Page VII.6-3 COMPARATORS WITH INTERNAL FEEDBACK Cross-Coupled Bistable VDD M3 M10 M11 M4 M8 M6 M1 M2 vO BIAS M5 M9 M7 VSS (1). Positive feedback gives hysteresis. (2). Also speeds up the propagation delay time. 1.0V -600m 2.0V 3.0V 4.0V 5.0V 6.0V -400m -200m 0m 200m EXAMPLE 7.4-1 COMPARATOR WITH HYSTERESIS 400m 600m Allen and Holberg - CMOS Analog Circuit Design Page VII.6-4 Allen and Holberg - CMOS Analog Circuit Design Page VII.6-5 AUTO ZEROING OF VOLTAGE COMPARATORS Model of the Comparator Including Offset + - IDEAL + - VOS Auto Zero Scheme-First Half of Cycle + - + IDEAL - CAZ VOS Auto Zero Scheme-Second Half of Cycle VIN + VOS + + VOS IDEAL - + 0V - + V - OS Allen and Holberg - CMOS Analog Circuit Design Page VII.6-6 GENERALIZED AUTO ZERO CONFIGURATION φ1 φ2 vIN+ + φ1 vIN- φ2 VOS +CAZ IDEAL + - - VOS φ1 Good for inverting or noninverting when the other terminal is not on ground. vOUT Allen and Holberg - CMOS Analog Circuit Design Page VII.6-7 Noninverting Auto-Zeroed Comparator φ1 φ2 φ1 vOUT vIN + CAZ φ2 φ1 Inverting Auto-Zeroed Comparator φ1 φ2 CAZ - vIN vOUT φ1 Use nonoverlapping, two-phase clock. + Allen and Holberg - CMOS Analog Circuit Design Page VII.6-1 VII.6 - HIGH SPEED COMPARATORS C oncept Question: For a given input change, what combination of first-order openloop comparators and a latch gives minimum propagation delay? + vIN - C1 C2 C3 Cn Latch Q Q n first-order, open-loop comparators with identical gains, A Concept: voltage High Output Level ∆ = input voltage change Latch n tn-1 v out = A [1 - (1 + (n-1)! )e-t/τ ] ∆ vout = e t/ τ ∆ A5∆ A4∆ A3 ∆ 5 4 3 v out = A2[1 - (1 + t)e -t/τ )] ∆ 2 v out = A(1-e-t/τ )∆ n=1 A2∆ A∆ t3 tL Time Propagation delay time = t3 + tL for n=3 Answer: tp(min) occurs when n=6 and A=2.72=e Implementation: n=3 and A≈6 gave nearly the same result with less area. [Ref: Doernberg et al., “A 10-bit 5 MSPS CMOS Two-Step FLASH ADC”JSSC April 1989 pp 241249] Allen and Holberg - CMOS Analog Circuit Design Page VII.6-2 HIGH SPEED COMPARATORS-CONT'D Conceptual Implementation- + vIN - + - + - + - - + - + - + Latch Q Q VDD Q FB Reset Q FB VB1 Offset and level shifting- vIN VB2 VSS vIN-VOS +- _ + VOS LATCH - + Allen and Holberg - CMOS Analog Circuit Design Page VII.7-1 VII.7 - COMPARATOR SUMMARY • Key performance parameters: Propagation time delay Resolving capability Input common mode swing Input offset voltage • Types of comparators: Open loop Regenerative Open loop and regenerative Charge balancing • Open loop comparator needs differential input and second stage • Systemative offset error is offset (using perfectly matched transistors) that is due to current mirror errors. • For fast comparators, keep all node swings at a minimum except for the output (current comparators?). • Key design equations: iD = KW 2 2L (vGS-VT) , vDS(sat) = 2iD K(W/L) , and gm = 2KWID L • Positive feedback is used for regenerative comparators. • Use autozeroing to remove offset voltages (charge injection is limit). • Fastest comparators using low-gain, fast open loop amplifiers cascaded with a latch. Allen and Holberg - CMOS Analog Circuit Design Page VII.0-1 VIII. SIMPLE CMOS OPERATIONAL AMPLIFIERS (OP AMPS) AND OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS (OTA'S) Contents VIII.1 VIII.2 VIII.3 Design Principles OTA Compensation Two-Stage CMOS OTA Design Organization Chapter 10 D/A and A/D Converters Chapter 11 Analog Systems SYSTEMS Chapter 7 CMOS Comparators Chapter 8 Simple CMOS Op Amps Chapter 9 High Performance OTA's COMPLEX CIRCUITS Chapter 5 CMOS Subcircuits Chapter 6 CMOS Amplifiers SIMPLE Chapter 2 CMOS Technology DEVICES Chapter 3 CMOS Device Modeling Chapter 4 Device Characterization Allen and Holberg - CMOS Analog Circuit Design Op Amp Characteristics Non-ideal model for an op amp V 1 R I b2 icm CMRR 2 e V R 2 2 V os V n R I n id C Ideal id + 1 R icm I b1 Boundary Conditions Process Specification Supply Voltage Supply Current Temperature Range Typical Specifications Gain Gainbandwidth Settling Time Slew Rate Input CMR CMRR PSRR Output Swing Output Resistance Offset Noise Layout Area Requirement See Tables 3.1-1 and 3.1-2 +5 V ±10% 100 µA 0 to 70°C ≥ 80 dB ≥ 10 MHz ≤ 0.1 µsec ≥ 2 V/µsec ≥ ±2 V ≥ 60 dB ≥ 60 dB ≥ 2 VP-P Capacitive load only ≤ ± 5 mV ≤ 50nV/ Hz at 1KHz ≤ 10,000 square µm out Allen and Holberg - CMOS Analog Circuit Design Frequency Response Av0 A v (s) = s s s (p − 1 ) (p − 1 ) (p − 1 ) . . . 1 2 3 -6dB/oct Gain, dB GB 0 dB ω1 Frequency 180 Phase (degrees) 90 Phase margin 0 Frequency -90 ω2 ω3 Allen and Holberg - CMOS Analog Circuit Design Power supply rejection ratio (PSRR): vout vin ( v ps =0) A vd(s) ∆VDD PSRR = · Avd(s) = Aps(s) = vout ∆vOUT vps ( v in=0) Common-mode input range (ICMR). Maximum common mode signal range over which the differential voltage gain of the op amp remains constant. Maximum and minimum output voltage swing. Slew rate: ∆vOUT Slew rate = max ∆t 10V 5V Output Voltage 0V -5V -10V 0µs Input Voltage 2µs 4µs Time 6µs 8µs 10µs Allen and Holberg - CMOS Analog Circuit Design Settling Time 1.4 1.2 Upper tolerance 1 Vout(t) Lower tolerance 0.8 0.6 Settling time 0.4 0.2 0 0 2 4 6 Time (sec) 8 10 12 14 Allen and Holberg - CMOS Analog Circuit Design Design Approach Design Specifications Iterate Analysis Simulation Modify Specifications: • Gain • Bandwidth • Output voltage swing • PSRR • Settling time • CMRR • Power dissipation • Noise • Supply voltage • Common-mode input range • Silicon area Allen and Holberg - CMOS Analog Circuit Design Design Strategy The design process involves two distinct activities: Architecture Design • Find an architecture already available and adapt it to present requirements • Create a new architecture that can meet requirements Component Design • Design transistor sizes • Design compensation network If available architectures do not meet requirements, then an existing architecture must be modified, or a new one designed. Once a satisfactory architecture has been obtained, then devices and the compensation network must be designed. Allen and Holberg - CMOS Analog Circuit Design Op Amp Architecture VDD M3 M4 M6 M1 M2 - + Compensation IBias M5 M7 vOUT Allen and Holberg - CMOS Analog Circuit Design Compensation In virtually all op amp applications, feedback will be applied around the amplifier. Therefore, stable performance requires that the amplifier be compensated. Essentially we desire that the loop gain be less than unity when the phase shift around the loop is greater than 135˚ β + IN Σ A OUT A = IN 1 + Aβ Goal: 1 + Aβ > 0 Rule of thumb: arg[Aβ] < 135˚ at mag[A β] = 1 OUT Allen and Holberg - CMOS Analog Circuit Design Graphical Illustration of Stability Requirements β =1 |Aβ| (dB) -6dB/oct GB 0 dB ω1 Frequency 180o Arg[Aβ] 90o 0o Frequency ω2 -12dB/oct Allen and Holberg - CMOS Analog Circuit Design Step Response of Two-Pole System Impact of placing ω2 at different locations: stability Date/Time run: 04/08/97 19:45:36 Temperature: 27.0 1.5V 3 2 1 1.0V ω1 = 1000 rps Case 1: ω2 = 1 x 106 rps 0.5V Case 2: ω2 = 0.5 x 106 rps Case 3: ω2 = 0.25 x 106 rps 0V 0s 5us 10us v(5) Time 15us 20us Allen and Holberg - CMOS Analog Circuit Design Types of Compensation 1. Miller - Use of a capacitor feeding back around a high-gain, inverting stage. • Miller capacitor only • Miller capacitor with an unity-gain buffer to block the forward path through the compensation capacitor. Can eliminate the RHP zero. • Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero. 2. Self compensating - Load capacitor compensates the op amp (later). 3. Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity. Allen and Holberg - CMOS Analog Circuit Design Miller Compensation VDD M3 M4 CM M1 M2 - M6 Cc + v OUT IBias C1 CL M7 M5 Small-signal model 1 gds2+g ds4 -v gm1 in 2 CM r ds1 + v1 - gm4v 1 1 gm3 1 gds6 +gds7 Cc + v g m2 in 2 + v2 C1 - CL vout gm6 v2 - Simplified small-signal model 1 gds2+gds4 + vin - 1 gds6+gds7 Cc + gm1vin v2 - + C1 gm6v2 CL vout - Allen and Holberg - CMOS Analog Circuit Design Analysis (gmI)(gmII)(RI)(RII)(1 - sCc/gmII) Vo(s) = Vin(s) 1 + s[RI(C1 + Cc) + RII(CL + Cc) + gmIIRIRIICc] + s2RIRII[C1CL + Cc(C1+ CL)] p1 ≅ g -1 mII RI RII Cc -gmIICc p2 ≅ C C + C C + C C 1L Lc 1c p2 ≅ -gmII CL z1 = gmII Cc where gmI = gm1 = gm2 RI = g 1 ds2+gds4 gmII = gm6 RII = g 1 ds6+gds7 Allen and Holberg - CMOS Analog Circuit Design Miller Compensation β =1 |Aβ| (dB) -6dB/oct Before compensation GB After compensation ω1 Frequency ω2 -12dB/oct 180o Before compensation Arg[Aβ] 90o 0o After compensation Phase margin Frequency Allen and Holberg - CMOS Analog Circuit Design Conditions for Stability • Unity-gainbandwith is given as: 1 gmI = C c gmIIRIRIICc GB = Av(0)·|p1| = ( gmIgmIIRIRII) · • The requirement for 45° phase margin is: ω ω ω - tan-1 - tan-1 = 45 ° z |p1| |p2| Arg[Aß] = ±180° - tan-1 Let ω = GB and assume that z ≥ 10GB, therefore we get, GB GB GB = 45 ° - tan-1 - tan-1 z |p1| |p2| ±180° - tan-1 or GB GB 135° ≈ tan-1(Av(0)) + tan-1 + tan-1(0.1) = 90 ° + tan-1 + 5.7° |p2| |p 2 | GB GB 39.3° ≈ tan -1 | ⇒ |p | = 0.818 ⇒ | p 2 | ≥ 1 .22GB |p2 2 • The requirement for 60° phase margin: | p 2 | ≥ 2 .2GB if z ≥ 1 0GB Allen and Holberg - CMOS Analog Circuit Design • If 60° phase margin is required, then the following relationships apply: gmII 10gmI Cc > Cc ⇒ g m II > 1 0g m I Furthermore, gmII 2.2gm I C2 > Cc which after substitution gives: C c > 0 .22C 2 Note: gmI = gm1 = gm2 and gmII = gm6 Allen and Holberg - CMOS Analog Circuit Design Phase margin = 45 degrees Phase margin = 60 degrees Parasitic pole, ω2, held constant while dominant pole, ω1, is moved. Allen and Holberg - CMOS Analog Circuit Design Eliminating RHP Zero M3 M4 M1 M6 Cc M2 RZ V OUT CII Vbias M7 M5 RZ + vin - Cc + gmI vin v2 + RI CI - gmII v2 VI sCc gmIVin + R + sCIVI + (VI − Vo) = 0 I 1 + s C cR z Vo sCc gmIIVI + R + sCIIVo + (Vo − VI) = 0 II 1 + s C cR z These equations can be solved to give Vo(s) a{1 − s[(Cc/gmII) − RzCc]} Vin(s) = 1 + bs + cs2 + ds3 where a = gmIgmIIRIRII b = (CII + Cc)RII + (CI + Cc)RI + gmIIRIRIICc + RzCc RII CII vout - Allen and Holberg - CMOS Analog Circuit Design c = [RIRII(CICII + CcCI + CcCII) + RzCc(RICI + RIICII)] d = RIRIIRzCICIICc If Rz is assumed to be less than RI or RII and the poles widely spaced, then the roots are p1 ≅ p2 ≅ −1 −1 ≅g R RC (1 + gmIIRII)RICc mII II I c −gmIICc −gmII ≅C CICII + CcCI + CcCII II −1 p3 = R C zI and z1 = 1 Cc(1/gmII − Rz) By setting Rz = 1/gmII The RHP zero moves to infinity Allen and Holberg - CMOS Analog Circuit Design Implementing Compensation Resistor M3 M4 M1 M2 M6 MZ Cc V OUT CII Vbias M7 M5 Allen and Holberg - CMOS Analog Circuit Design Two-Stage Operational Amplifier Design VDD M6 M3 M4 Cc vout vin + M1 CL M2 + VBias - M7 M5 VSS Figure 6.3-1 Schematic of an unbuffered, two-stage CMOS op amp Important with an n-channel input pair. relationships: gm1 = gm2 = gmI, gm6 = gmII, gds2 + gds4 = GI, and gds6 + gds7 = GII. Slew rate SR = I5 Cc First-stage gain Av1 = (1) gm1 gds2 + gds4 Second-stage gain Av2 = Gain-bandwidth GB = Output pole p2 = RHP zero z1 = = gm6 gds6 + gds7 2gm1 I5(λ 2 + λ 4) = gm6 I6(λ 6 + λ 7) gm1 Cc (3) (4) −gm6 CL (5) gm6 Cc Positive CMR Vin(max) = VDD − (2) (6) I5 β3 − |VT03|(max) + VT1(min)) (7) Allen and Holberg - CMOS Analog Circuit Design I5 Negative CMR Vin(min) = VSS + Saturation voltageVDS(sat) = β1 + VT1(max) + VDS5(sat) 2IDS (8) (9) β All transistors are in saturation for the above relationships. The following design procedure assumes that specifications for the following parameters are given. 1. 2. 3. 4. 5. 6. 7. Gain at dc, Av(0) Gain-bandwidth, GB Input common-mode range, ICMR Load Capacitance, CL Slew-rate, SR Output voltage swing Power dissipation, Pdiss Choose a device length to establish of the channel-length modulation parameter λ. Design the compensation capacitor Cc. It was shown that placing the loading pole p2 2.2 times higher than the GB permitted a 60° phase margin (assuming that the RHP zero z1 is placed at or beyond ten times GB). This results in the following requirement for the minimum value for Cc. Cc > (2.2/10) CL Next, determine the minimum value for the tail current I5, based upon slew-rate requirements. Using Eq. (1), the value for I5 is determined to be I5 = SR (Cc) If the slew-rate specification is not given, then one can choose a value based upon settlingtime requirements. Determine a value that is roughly ten times faster than the settling-time specification, assuming that the output slews approximately one-half of the supply rail. The value of I5 resulting from this calculation can be changed later if need be. The aspect ratio of M3 can now be determined by using the requirement for positive input common-mode range. The following design equation for (W/L)3 was derived from Eq. (7). S 3 = ( W /L )3 = I5 (K'3) [VDD − Vin(max) − |VT03|(max) + VT1(min)]2 If the value determined for (W/L)3 is less than one, then it should be increased to a value that minimizes the product of W and L. This minimizes the area of the gate region, which Allen and Holberg - CMOS Analog Circuit Design in turn reduces the gate capacitance. This gate capacitance will affect a pole-zero pair which causes a small degradation in phase margin. Requirements for the transconductance of the input transistors can be determined from knowledge of Cc and GB. The transconductance gm2 can be calculated using the following equation gm1 = GB (Cc) The aspect ratio (W/L)1 is directly obtainable from gm1 as shown below g2 1 m S1 = (W/L)1 = (K' )(I ) 25 Enough information is now available to calculate the saturation voltage of transistor M5. Using the negative ICMR equation, calculate VDS5 using the following relationship derived from Eq. (8). I5 VDS5 = Vin(min) − VSS − β 1 1/2 − VT1(max) If the value for VDS5 is less than about 100 mV then the possibility of a rather large (W/L)5 may result. This may not be acceptable. If the value for VDS5 is less than zero, then the ICMR specification may be too stringent. To solve this problem, I5 can be reduced or (W/L)1 increased. The effects of these changes must be accounted for in previous design steps. One must iterate until the desired result is achieved. With VDS5 determined, (W/L)5 can be extracted using Eq. (9) in the following way S 5 = ( W /L )5 = 2(I5) K'5(VDS5)2 For a phase margin of 60°, the location of the loading pole was assumed to be placed at 2.2 times GB. Based upon this assumption and the relationship for |p2| in Eq. (5), the transconductance gm6 can be determined using the following relationship gm6 = 2.2(gm2)(CL/Cc) Since S3 is known as well as gm6 and gm3, assuming balanced conditions, gm6 S6 = S3 g m3 I6 can be calculated from the consideration of the “proper mirroring” of first-stage the current mirror load of Fig. 6.3-1. For accurate current mirroring, we want VSD3 to be equal to VSD4. This will occur if VSG4 is equal to VSG6. VSG4 will be equal to VSG6 if Allen and Holberg - CMOS Analog Circuit Design (W/L)6 S 6 I6 = (W/L) I1 = S I1 4 4 Choose the larger of these two values for I6 (Eq. 19 or Eq. 20). If the larger value is found in Eq (19), then (W/L)6 must be increased to satisfy Eq. (20). If the larger value is found in Eq. (20), then no other adjustments must be made. One also should check the power dissipation requirements since I6 will most likely determine the majority of the power dissipation. The device size of M7 can be determined from the balance equation given below I6 I6 S7 = (W/L)7 = (W/L)5 = S5 I5 I5 The first-cut design of all W/L ratios are now complete. Fig. 6.3-2 illustrates the above design procedure showing the various design relationships and where they apply in the two-stage CMOS op amp. Max. ICMR and/or p3 VSG4 - M3 vin + VDD + + VSG6 - M4 Cc Cc ≈ 0.2CL (PM = 60°) M2 Min. ICMR I5 + VBias - M5 M6 I6 g GB = m1 Cc M1 Vout(max) I5 = SR·Cc gm6 or Proper Mirroring VSG4=VSG6 vout CL Vout(min) M7 VSS Figure 6.3-2 Illustration of the design relationships and the circuit for a two-stage CMOS op amp. At this point in the design procedure, the total amplifier gain must be checked against the specifications. Av = (2)(gm2)(gm6) I5(λ 2 + λ 3)I6(λ 6 + λ 7) If the gain is too low, a number of things can be adjusted. The best way to do this is to use the table below, which shows the effects of various device sizes and currents on the Allen and Holberg - CMOS Analog Circuit Design different parameters generally specified. Each adjustment may require another pass through this design procedure in order to insure that all specifications have been met. Table 6.3-2 summarizes the above design procedure. Dependencies of device performance on various parameters Increase DC Gain Increase GB Increase RHP Zero Increase Slew Rate Increase CL Drain Current I5 I7 (↓)1/2 (↓)1/2 M1 and M2 W/L L (↑)1/2 ↑ (↑)1/2 (↑)1/2 (↑)1/2 ↑ M3 and M4 W L ↑ Inverter Inverter Comp. Load Cap.. W6/L6 W 7 L7 Cc ↑ (↑)1/2 (↑)1/2 ↓ ↓ ↓ ↓ Allen and Holberg - CMOS Analog Circuit Design Design Procedure: This design procedure assumes that the gain at dc (Av), unity gain bandwidth (GB), input common mode range (Vin(min) and Vin(max)), load capacitance (CL), slew rate (SR ), settling time (Ts), output voltage swing (Vout(max) and Vout(min)), and power dissipation (Pdiss) are given. 1. 2. Choose the smallest device length which will keep the channel modulation parameter constant and give good matching for current mirrors. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60° phase margin we use the following relationship. This assumes that z ≥ 10GB. Cc > 0.22 CL 3. Determine the minimum value for the “tail current” (I5) from the largest of the two values. I5 = S R .C c VDD + |VSS| I5 ≅ 10 . 2 Ts 4. Design for S3 from the maximum input voltage specification. S3 = 5. I5 K'3[VDD − Vin(max) − |VT03|(max) + VT1(min)]2 ≥1 Verify that the pole of M3 due to Cgs3 and Cgs4 (=0.67W3L3Cox) will not be dominant by assuming it to be greater than 10 GB gm3 2Cgs3 > 10GB . 6. Design for S1 (S2) to achieve the desired GB. 2 gm1 = GB . Cc ⇒ S2 = 7. gm2 K'2I5 Design for S5 from the minimum input voltage. First calculate VDS5(sat) then find S5. VDS5(sat) = Vin(min) − VSS − S5 = 2I5 K'5[VDS5(sat)]2 I5 β1 − VT1(max) ≥ 100 mV Allen and Holberg - CMOS Analog Circuit Design 8. Find gm6 and S6 by the relationship relating to phase margin, load, and compensation capacitors, and the balance condition. gm6 = 2.2gm2(CL/Cc) gm6 S6 = S3 g m3 9. Calculate I6 : I6 = (S6/S4)I4 = (S6/S4)(I5/2) 10. Design S7 to achieve the desired current ratios between I5 and I6. S7 = (I6/I5)S5 11. Check gain and power dissipation specifications. Av = 2gm2gm6 I5(λ 2 + λ 3)I6(λ 6 + λ 7) Pdiss = (I5 + I6)(VDD + |VSS|) 12. If the gain specification is not met, then the currents, I5 and I6, can be decreased or the W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked to insure that they have been satisfied. If the power dissipation is too high, then one can only reduce the currents I5 and I6. Reduction of currents will probably necessitate increase of some of the W/L ratios in order to satisfy input and output swings. 13. Simulate the circuit to check to see that all specifications are met. Allen and Holberg - CMOS Analog Circuit Design Example: Design of a Two-Stage Op Amp Using the material and device parameters given in Tables 3.1-1 and 3.1-2, design an amplifier similar to that shown in Fig. 6.3-1 that meets the following specifications. Assume the channel length is to be 1µm. Av > 3000V/V VDD = 2.5V VSS = -2.5V GB = 5MHz CL = 10pF SR > 10V/µs Vout range = ±2V ICMR = -1 to 2V Pdiss ≤ 2mW Solution Calculate the minimum value of the compensation capacitor Cc, Cc > (2.2/10)(10 pF) = 2.2 pF Choose Cc as 3pF. Using the slew-rate specification and Cc calculate I5. I5 = (3 × 10-12)(10 × 106) = 30 µA Next calculate (W/L)3 using ICMR requirements. (W/L)3 = 30 × 10-6 = 15 (50 × 10-6)[2.5 − 2 − .85 + 0.55]2 gm3 = 2 × 50x10-6 x15x10-6 × 15 = 150µS Therefore (W/L)3 = (W/L)4 = 15 Check the value of the mirror pole, p3, to make sure that it is in fact greater than 10GB. Assume the Cox = 0.4fF/µm2. The mirror pole can be found as -gm3 - 2K’pS3I3 p3 ≈ 2C = 2(0.667)W L C = 15.75x109(rads/sec) gs3 3 3 ox or 2.98 GHz. Thus, p3, is not of concern in this design because p3 >> 10GB. The next step in the design is to calculate gm1 gm1 = (5 × 106)(2π)(3 × 10-12) = 94.25 µS Therefore, (W/L)1 is gm12 (94.25)2 (W/L)1 = (W/L)2 = 2K’ I = 2·110·15 = 2.79 ≈ 3.0 N1 Next calculate VDS5 Allen and Holberg - CMOS Analog Circuit Design VDS5 = (−1) − (−2.5) − 30 × 10-6 - .85 = 0.35V 110 × 10-6·3 Using VDS5 calculate (W/L)5 from Eq. (16) (W/L)5 = 2(30 × 10-6) = 4.49 ≈ 4.5 (50 × 10-6)(0.35)2 From Eq. (20) of Sec. 6.2, we know that gm6 ≥ 10gm1 ≥ 942.5µS Assuming that gm6 = 942.5µS (W/L)6 = 15 942.5 × 10-6 = 94.25 150 × 10-6 Using the equations for proper mirroring, I6 is determined to be I6 = (15 × 10-6)(94.25/15) = 94.25 µA Finally, calculate (W/L)7 94.25 × 10-6 (W/L)7 = 4.5 ≈ 14.14 30 × 10-6 Check the Vout(min) specification although the W/L of M7 is so large that this is probably not necessary. The value of Vout(min) is Vmin(out) = VDS7(sat) = 2 × 94.25 = 0.348V 110 × 14.14 which is much less than required. At this point, the first-cut design is complete. Examining the results shows that the large value of M7 is due to the large value of M5 which in turn is due to a tight specification on the negative input common mode range. To reduce these values the specification should be loosened or a different architecture (i.e. p-channel input pair) examined. Now check to see that the gain specification has been met Av = (2)(94.25 × 10-6)(942.5 × 10-6) = 19,240 30 × 10-6(.04 + .05)38 × 10-6(.04 + .05) which meets specifications. Allen and Holberg - CMOS Analog Circuit Design IX. HIGH PERFORMANCE CMOS AMPLIFIERS Contents IX.1 IX.2 IX.3 IX.4 IX.5 IX.6 IX.7 Improving The Two-Stage Architecture Two-stage Cascode Architecture Folded Cascode Architecture Differential Output Architecture (Class AB) Low power amplifiers Dynamically biased amplifiers Organization Chapter 10 D/A and A/D Converters Chapter 11 Analog Systems SYSTEMS Chapter 7 CMOS Comparators Chapter 8 Simple CMOS Op Amps Chapter 9 High Performance OTA's COMPLEX CIRCUITS Chapter 5 CMOS Subcircuits Chapter 6 CMOS Amplifiers SIMPLE Chapter 2 CMOS Technology DEVICES Chapter 3 CMOS Device Modeling Chapter 4 Device Characterization Allen and Holberg - CMOS Analog Circuit Design IX.1 IMPROVING THE TWO-STAGE ARCHITECTURE Amplifiers Using an MOS Output Stage PUSH-PULL CMOS OTA This amplifier is a simple extension of the seven-transistor OTA studied in Section 8. VDD M9 VDD M7 VDD vOUT M1 - VDD M2 + Cc CL M8 M6 M4 M3 small-signal equivalent circuit: Cc vout + gm1 vi C1 r1 v1 gm6 v1 CL r2 - 1 1 where gm1 = gm2, r1 = g , r2 = g ds2 + g ds4 ds6 + g ds7 gm1 Ai vi 2 Allen and Holberg - CMOS Analog Circuit Design Amplifiers Using an MOS Output Stage - Continued Network equations: [g1 + s(C1 + CL)]v1 - sCcv2 = gm1vi gm1AIvi 2 i7 AI is the current gain from M1 to M7: AI = i 1 -g m6 z= AI - 1Cc 2 -g1g2 p1 ≈ gm6Cc -g m6 p2 ≈ C L gm1gm6 AV ≈ g g 12 [g5 + sCc]v1 + [g2 + s(Cc + CL)]v2 = To guarantee that the zero stays in the left-half plane, AI > 2 Allen and Holberg - CMOS Analog Circuit Design Amplifiers Using an MOS Output Stage - Continued Example: VDD VDD VDD M9 - M7 M1 VDD M2 VDD M9 VDD + M7 M1 - Cc + M2 Cc CL CL M8 M6 M3 M6 M4 M4 M3 Push-Pull (AI ≈ 3 ) Standard (AI = 0) 140 120 100 Gain(db) 80 Push-Pull phase 60 Standard gain 40 Push-Pull gain 20 Standard phase 0 -20 1 10 2 10 3 10 VDD 4 10 5 10 6 10 Frequency 7 10 8 10 9 10 Allen and Holberg - CMOS Analog Circuit Design IX.2 Two-Stage Cascode Architecture Why Cascode Op Amps? • Control the frequency behavior • Increase PSRR • Simplifies design Where is the Cascode Technique Applied? • First stage Good noise performance Requires level translation to second stage Requires Miller compensation • Second stage Self compensating Reduces the efficiency of the Miller compensation Increases PSRR Allen and Holberg - CMOS Analog Circuit Design Power Supply Rejection Ratio (PSRR) Definition: + vdd - VDD - + + vin + + vout - vss - VSS - vout vin (vdd=0) A (v =0) + = v dd PSRR Add(vin=0) = vout vdd (vin=0) Calculation of PSRR: + vdd + Addvdd VDD v1 - - vout + VSS => vout v2 Av (v1 -v2 ) K vout = Addvdd + A v(v1-v2) = A ddvdd - Avvout vout(1 + Av) = A ddvdd Extends bandwidth beyond GB ↓ vout Add A dd 1 =1+A ≈ A = vdd PSRR+ v v vout KAdd A dd = 1+KA ≈ A vdd v v Allen and Holberg - CMOS Analog Circuit Design Intuitive Interpretation of Positive PSRR for the Two-Stage OTA + + vdd VDD - - 1.) The M7 current sink causes VGS6 to act like a battery. M3 2.) Therefore, vdd M4 couples from the source M6 M1 to gate of M6. Cc M2 - vout + 3.) The path to the output is through any capacitance M7 M5 from gate to drain of M6. + VBias VSS + - 4.) Resultant circuit model- + vdd vout Cc Rout - Must reduce C c ! Vout Vdd 0dB -60 to -80dB 1 Rout Cc ω Other sources of PSRR beside C c Allen and Holberg - CMOS Analog Circuit Design Intuitive Interpretation of the Negative PSRR for the Two-Stage OTA + VDD - M3 M4 M6 M1 Cc M2 - + vout M7 M5 + VBias + ? vss VSS + - Two mechanisms of vss injection: iss M5 or M7 + + VBias - M5 + vss VBias vss - VSS + VSS Transconductance injection + + - Capacitance injection Allen and Holberg - CMOS Analog Circuit Design Intuitive Interpretation of the Negative PSRR for the Two-Stage OTA Continued Transconductance injection: Vout Vss Path through the input stage: Not important as long as CMRR is high. 20 to 40 dB Path through the output stage: vout ≈ issRout = gm7 vssRout 0dB 1 Rout Cout vout vss = g m7Rout Frequency dependence 1 Rout → Rout|| sCout Capacitance injection: + vss vout Cgd7 Rout Vout Vss 0dB -60 to -80dB Reduce Cgd7! 1 Rout C gd7 ω First stage transconductance injection ω Allen and Holberg - CMOS Analog Circuit Design Problems with the two-stage OTA: • Insufficient gain • Poor stability for large load capacitance • Poor PSRR These problems can be addressed using various cascode structures. We will consider several approaches: • Cascoding the first stage • Cascoding the second stage • Folded cascode Allen and Holberg - CMOS Analog Circuit Design First Stage C ascode VDD M3 VDD VBP M4 VDD MC2 VDD VBN MC3 VO1 MC1 + M1 M2 VBIAS VSS ro1 ≈ (gmc2rdsc2)rds4 || (gmc1rdsc1)rds2 Gain ≈ gm2ro1 • Overall gain increased by ≈ gmcrdsc 2 • Requires voltage translation to drive next stage • Requires additional biasing for cascode devices • Common-mode problem at drains of M1 and M2 Allen and Holberg - CMOS Analog Circuit Design First Stage Cascode - C ontinued Common-mode improvement: VDD M3 VDD M4 VDD ICM VBP MC2 MC3 VDD MC1 M9 + VO1 - M1 M2 VBIAS VSS Common-mode circuitry (M9) maintains Vds of M1 and M2 A V = gm1ro1 ro1 ≈ (gmc2rdsc2)rds4 || (gmc1rdsc1)rds2 -1 p1 ≈ C r L o1 GB ≈ A V|p1| ≈ gm1 CL Output range of this amplifier is poor when used by itself. It needs an output stage to be practical. Allen and Holberg - CMOS Analog Circuit Design First Stage Cascode - C ontinued Implementation of ICM VDD M4 M3 ICM ICM VBP VDD MC2 VSS VSS VSS MC1 MC3 vin 2 -vin vin 22 VSS VSS -vin 2 VSS M2 M1 I5 +ICM VSS Allen and Holberg - CMOS Analog Circuit Design Level Translator for First Stage Cascode VDD M4 MT2 M6 MC2 MT1 MC1 Vo VSS M2 VBIAS M5 VSS M7 Allen and Holberg - CMOS Analog Circuit Design Improved PSRR For Two-Stage O TA Use cascode to reject Cc feedforward VDD M3 M6 M8 VB1 - M4 Cc M9 + M2 M1 vOUT M5 VB2 M7 VSS +PSRR is reduced by M9 Disadvantage Miller pole is larger because R1 ≈ 1 gm9 positive input common mode range is restricted Allen and Holberg - CMOS Analog Circuit Design Complete Two Stage Cascode VDD M4 M3 MT2 VBP M6 MC2 MT1 ICM MC3 MC1 Vo VSS M9 M1 M2 M7 VBIAS M5 VSS Allen and Holberg - CMOS Analog Circuit Design Second Stage Cascode VDD M3 M4 M6 VBP Comp M2 M1 VBN MC6 Vo MC5 M7 VBIAS M5 VSS Allen and Holberg - CMOS Analog Circuit Design LOAD COMPENSATED CASCODE AMPLIFIER VDD VDD M9 M3 M4 VDD M6 VDD MC2 VBP MC3 VBP VDD - + M2 M1 M5 I5 VDD VDD MC1 VBN VSS VBIAS CL M8 M7 VSS gm 2 A V1 = g m4 1 A V2 = 2 ( g m6 + g m9 )R o where gm2 AV = 2(g ) (g m6 + gm9) Ro m4 Ro ≈ (g mc2rdsc2)rds6 || (gmc1rdsc1)rds7 and M7 = M8 Or, gm1 +g m2 KR o 2 AV = where K= W6/L6 W 9/L 9 W4/L4 = W3/L3 Allen and Holberg - CMOS Analog Circuit Design Design E xample Pertinent design equations: iOUT SR = C L AV = gm2 2(gm4) (gm6 + gm7 ) ro GB = g m2 (g m6 + g m7 ) 2(gm4)CL Vin(max) = VDD - I5 ß3 - |VT3|(max) + V T1(min) Vin(min) = VSS + VDS5 + Specifications: VDD = -VSS = 5V SR = 5V/µs into CL = 50pf GB = 5 MHz AV > 5000 CMR = ±3V Output swing = ±3V I5 ß1 + VT1(max) Allen and Holberg - CMOS Analog Circuit Design Design P rocedure 1.) Design for maximum source/sink current Isource/sink = C L(SR) = 50pf(5V/µs) = 250 µA 2.) Note that S6 Max. IOUT (source) = S I5 4 Max. IOUT (Sink) = Max. IOUT (source) if S3 = S 4, S9 = S6 and S7 = S 8 3.) Choose I 5 = 1 00 µ A ∴ S 9 = S 6 = 2 .5 S 4 = 2 .5 S 3 4 .) Design for ± 3V output capability a.) Negative peak Let VDSC1(sat.) = V DS7(sat.) = 1V under negative peak conditions, IC1 = I 7 = 250 µA Divide 2V equally, ∴ 2V = 2I7 + KN'S7 ∴ S 7 = S C1 = 2 9.4 2IC1 =2 KN'SC1 2I7 KN'S7 = 2 -> S 8 = S 7 = 2 9.4 5 00 µ A 17 µ A/V 2 S 7 Allen and Holberg - CMOS Analog Circuit Design b.) Positive peak, divide voltage equally, VSD6 = VSDC2 = 1V , --> 2V = ∴ S 6 = S C2 = 6 2.5 2I6 + KP'S6 2IC2 =2 KP'SC2 2I6 KP'S6 --> S 3 = S 4 = 2 5 5 .) Design of VBP and V BN a.) VBN (Assume max. I OUT (sink) conditions) IOUT(sink) = 250 µA MC1 VBN -3 -5V VDSC1 = VGSC1 - V TC1 (ignoring bulk effects) -4 1 = VGSC1 -1 --> VGSC1 = 2V ∴ V BN = - 2V M7 -5 b.) VBP (Assume max. IOUT (source) conditions) +5V +4 VDSC2 = VGSC2 - |V TC2| (ignoring bulk effects) VSGC2 = 2V ∴ V BP = + 2V VBP MC2 IOUT(source) = 250 µA +3V Allen and Holberg - CMOS Analog Circuit Design 6.) Check max. Vin influence on S3 (S4) I5 ß3 - |VT03|max + VT1(min) Vin (max) = VDD +3 = +5 S3 = 1 00 µ A - 1.2 + 0.8 KP'S3 1 00 µ A = 4.88 (Use S 3 = S4 = 25) µA 8 2 ( 1.6V) 2 V With S 3 = 25, V in (max) = 3.89V which exceeds the specification. 7.) Find gm1 (gm2) a.) AV specification gm1 g m6 + g m 7 R II AV = gm4 2 gm4 = 2I4Kp'S4 = 141.1 µs gm6 = 2I6KP'S6 = 353.5 µs gm7 = 2I7KN'S7 = 353.5 µs gmc1 = gm7 gmc2 = gm6 1 rds6 = rdsc2 = I λ = 0.4 M Ω 6P 1 rds7 = rdsc1 = I7λΝ = 0.8 M Ω RII ≈ (gmc1rdsc1rds7) || (gmc2rdsc2rds6) = 45.25 MΩ gm1 707 µ s ( 226.24 M Ω | | 56.56 M Ω) > 5000 V/V ∴ 141.1 2 ∴ gm1 > 44 µs Allen and Holberg - CMOS Analog Circuit Design b.) GB specification GB = g m1 (g m6 + g m7 ) (50pF) = 10π.10 6 rps 2gm4 gm1 = (10 π.106)(141.1.10-6)(50.10-12) = 627 µS 707.10-6/2 gm 2 = 231 ∴ S 1 = S2 = I5K N ' gm1gm6+gm7 627 707µS R II = gm4 2 141.1 2 (45.25M Ω) = 71,080 8.) Find S5 from Vin (min) AV = Vin (min) = VSS + VDS5 + -3 = -5 + VDS5 + V DS5 = 0.8 - 1 00 µ A + 1.2 µA 17 2 S 1 V 100 = 0.8 - 0.1596 = 0.641 (17)(231) VDS5 (sat) = 0.641 = S5 = I5 ß1 + VT1(max) 2 (100 µ A) µA (17 2 )S5 V 2(100µA) = 28.6 17µA/V 2(0.641)2 9.) VBIAS KN'.28.6 I5 = ( V BIAS + 5 - 1) 2 = 100 µA 2 VBIAS = 0.411 - 4 = -3.359V Allen and Holberg - CMOS Analog Circuit Design 10.) Summary of design S1 = S2 = 231 S3 = S4 = 25 S5 = 28.6 S6 = S9 = SC2 = SC3 = 62.5 S7 = S8 = SC1 = 29.4 VBP = 2V VBN = -2V VBIAS = -3.359V 11.) Check on power dissipation Pdiss = 10(I8 + I5 + I7) = 10(125µA + 100µA + 125µA) = 3.5mW 12.) Design W's for lateral diffusion and simulate Allen and Holberg - CMOS Analog Circuit Design X.3 FOLDED CASCODE ARCHITECTURE Principle VDD 1.5 I 1.5 I VBP M3 M4 I v+ IN M1 M2 vIN vout =gm1 Rout vin I M5 M6 M7 M8 I VSS Currents in upper current sinks must be greater than I to avoid zero current in the cascode mirror (M5-M8). Advantages Good input CMR. Good frequency response. Self compensating. Allen and Holberg - CMOS Analog Circuit Design Folded Cascode OP Amp VDD VB3 M4 M3 + - VB3 M14 M2 M1 V OUT M9 M8 Cc M16 VB1 M5 M15 VB2 M11 M10 M13 M12 VSS High gain, High speed, cascode amp GB ≈ 10 MHz, AVDC ≈ 100 dB Allen and Holberg - CMOS Analog Circuit Design XI. 4 DIFFERENTIAL OUTPUT OTA'S Implementation Using Two Differential-In, Singled-Ended Op Amps + + R - R + - + Conceptual Implementation of Differential In-Out OP Amp VDD VDD + VDD VBIAS Vin - - Vout + CL CL Common mode feedback VSS Allen and Holberg - CMOS Analog Circuit Design Schematic of a Fully Differential In-Out, FoldedCascode Op Amp VDD = +5V MP1A VBIAS1 MP1 MP2A VDD VDD VBIAS2 MP2 vOUT + CL + CL vIN VSS - MN2A VSS VBIAS3 MN2 MN1 VSS VSS MN1A VSS VBIAS4 MN3 MN3A VSS = -5V Allen and Holberg - CMOS Analog Circuit Design Evolution of Class AB Amplifier VDD VDD VB2 v+ IN vIN vOUT vOUT v+ IN vIN VB1 VSS VSS combine M12 M11 VB2 v+ IN M1 M2 vIN v+ IN M3 M4 vIN VB1 M10 M17 M18 M9 M14 M13 Problem: DC levels of input voltages incompatible Allen and Holberg - CMOS Analog Circuit Design M17 M12 M14 M11 M5 v+ OUT M6 v+ IN M1 M3 M7 vIN M2 M4 vOUT M8 I I M18 M10 M13 M9 DC problem solved, but amplifier has low gain and requires CM feedback M17 M12 M14 M11 VB3 VB1 M5 v+ OUT M6 v+ IN M1 VB2 M7 M3 M4 VB4 M8 vOUT M15 I I M18 vIN M2 M16 M10 Gain improved using cascode M9 M13 Allen and Holberg - CMOS Analog Circuit Design IX.5 LOW POWER AMPLIFIERS General Objective is to minimize the dc power dissipation. Typical applications are: 1. Battery powered circuits. 2. Biomedical instrumentation. 3. Low power analog "VLSI." Weak Inversion or Subthreshold Operation Drain current qvGS W iD = I D exp nkT ( 1 + lv D S) L Small signal parameters qiD gm = nkT , rds ≈ (λ iD )-1 Device characteristics iD iD square law 100nA 100nA weak inversion vGS < VT 1 2 vDS exponential VT vGS Allen and Holberg - CMOS Analog Circuit Design Op Amp Operating in Weak Inversion Consider the two-stage op amp with reduced currents and power supplieds, AV = gm2 gm6 1 = n2n6( kT/q) 2( l2+l4) ( l6+l7) ( gds2+gds4) ( gds6+gds7) where, gm1 ID1 GB = C = (n kT/q)C 1 and 2ID1 n1kT SR = C = 2GB q VDD M3 M4 M6 C M1 M2 M7 M5 VSS Allen and Holberg - CMOS Analog Circuit Design Design Example Calculate the gain, unity-gain bandwidth, and slew rate of the previous two-stage op amp used in weak inversion if: ID5 = 200nA nP = 1.5 λP = 0.02V-1 L = 10 µm nN = 2.5 λN = 0.01V-1 C = 5pF T = 27˚C 1 AV = (1.5)(2.5)(0.026)(2)(0.1+0.02)(0.01+0.02) = 5698 GB = 100.10-9 = 307.69Krps or 48.97KHz (2.5)(0.026)(5.10-12) SR = 2(153.85.103)(2.5)(0.026) = 0.04V/µs If V DD = -V SS = 2.5, the power dissipation is 0.2µW assuming ID7 = I D5. Allen and Holberg - CMOS Analog Circuit Design Push-Pull Micropower Op Amp First stage clamped (low gain, low bias current)VDD M3 M4 M8 M6 M2 M1 CC VB M5 M7 M9 VSS Gain enhancement for Push-Pull Micropower Op Amp M11 M3 M10 M12 M4 M8 M6 M2 M1 CC VB M5 M13 M7 M9 VSS Allen and Holberg - CMOS Analog Circuit Design Push-Pull Cascode Micropower Op Amp VDD M3 M4 M8 M6 M1 M2 VB1 VDD M10 VB2 VB M5 VSS M11 M7 M9 VSS 1 1 +n nN P AV = 2 2 n P + λ N 2 n N 2 ) ≈ 10,000 Vt ( λ P self-compensating Low power << 1 µW CC Allen and Holberg - CMOS Analog Circuit Design Micropower Op Amp VDD M5 M9 M6 M7 M8 va v1 M10 vb M3 M4 M16 M15 100nA v+ 2 vo M17 M2 VBIAS M18 M19 M14 M12 M11 120nA 20nA 20nA VSS Pdiss = |VDD -VSS|(260nA) vo = vagm9ro - vbgm10ro ≈ g m9ro(va - vb) ; gm9 = gm10 where ro ≈ (rds10gm18rds18)||(rds12gm19rds19) and nP 1 + k (va - vb) = va - vb = n 1 - k ( v 2 - v 1 ) N (See following pages) Allen and Holberg - CMOS Analog Circuit Design Small-Signal Analysis va vb 1 gm5 gm3 v1 gm8 vb 1 gm6 gm7 va gm3 g m8 va = -v1 g - vb g m5 m5 gm4 g m7 vb = -v2 - va g gm6 m6 gm3 v1gm5 v2gm4 gm6 va = = gm3 v1g gm8 -g gm4 v2g -1 -1 gm8 -g gm7 -g -1 m5 m6 m4 m5 m5 -1 gm8 -g gm7 -g -1 m4 m5 va v b gm 3 g m4 g m 8 -v1 g + v2 g g m5 m5 m6 = g m7 g m 8 1gm5 gm6 gm4 v2 Allen and Holberg - CMOS Analog Circuit Design vb = v a - vb = -1 gm3 v1g gm7 -g gm4 v2g -1 gm8 -g gm7 -g -1 m6 m5 m4 m6 m5 gm 4 g m3 g m 7 -v2 g + v1 g g m6 m5 m6 = g m7 g m 8 1gm5 gm6 gm3 g m4 g m 8 gm4 g m3 g m 7 -v1 + v 2 g g - -v2g + v 1 g g gm5 m5 m6 m6 m5 m6 g m7 g m 8 1- g g m5 m4 gm3 = gm4 = gmI ; gm5 = gm6 = gmII ; gm7 = gm8 = gmIII Then gmI g mI g mIII gmI g mI g mIII -v1 + v2 - -v2 + v1 gmII gmII2 gmII gmII2 v a - vb = g mIII 2 1- Define: gmII2 gmIII gmII = k gmI v 2 - v1) g ( 1 + k) ( mII = ( v 2 - v1) v a - vb = 1 - k2 v a - vb = gmI gmII 1-k gmI 1 gmII 1 - k ( v 2 - v 1 ) Consider dc currents under balanced condititions: I 4 = I6 + I7 I 3 = I5 + I8 Allen and Holberg - CMOS Analog Circuit Design S8 S7 I 8 = I6 S ; I 7 = I 5 S 6 5 I8 S 8 ⇒ in W.I. gm is proportional to I I6 = S6 I 8 S8 I 7 S7 = S = k; I = S = k I6 6 5 5 Since under balanced conditions I 3 = I4 ; I4 = I5 I4 = I6 (1 + k) I3 = I5 (1 + k) Again, since gm ∝ I in weak inversion, then gm4 ∝ I 6(1 + k) or gm4 = I6 kT (1 + k) nN q and gm3 ∝ I5(1 + k) since gm3 = gm4 = gmI ⇒ gmI = Also gm4 = gmII = I6 kT nN q then nP gmI = n (1 + k) gmII N I6 k T (1 + k) nN q Allen and Holberg - CMOS Analog Circuit Design finally: nP 1 + k ( v 2 - v 1 ) v a - vb = n N 1 - k 1+k ≈ 1 - k ( v 2 - v1) Therefore, 1+k vo = gm9 ro 1-k vid Allen and Holberg - CMOS Analog Circuit Design OTA CURRENT OVERDRIVE Need large sinking and source currents without having to have large quiescent currents. One possible solution uses "tail current boosting" Assume that S 3 = S4 = S11 = S13, S18 = AS17, S15 = S16 = S17 = .. M11 I1 - I2 M1 I1 I2 M2 I2 + I2 +I1 +A I2 -I1 I1 M15 M13 M4 M3 A I2 -I1 I2 -I1 M16 M17 M18 W18 = AW17 L18 L17 M9 I10 I19 ≈ 0 M10 M19 Allen and Holberg - CMOS Analog Circuit Design Principle in Achieving Current Overdrive Differential amplifier transconductance characteristics iD I10 (overdrive) I10 (normal) I10 (overdrive) 2 I10 (normal) 2 vIN 0 - I10 (overdrive) B - I10 (overdrive) B I10 (normal) B I10 (normal) B Positive feedback I10 iOUT (max/min) ≈ 1 - Loop gain = I10 g m 1 8 gm 1 3 1- g m17 gm14 = I10 gm 1 3 1- g A m9 Allen and Holberg - CMOS Analog Circuit Design A Dynamically Biased Micropower Op Amp VDD M12 M8 M13 M3 M4 M11 I1 M5A I2 M1 M14 M2 + VBP M5B vOUT VBN M6B I10 M7 M15 M16 M17 M18 M9 M10 M19 M20 M21 M22 M6A VSS Allen and Holberg - CMOS Analog Circuit Design Parametric Overdrive Curves for Dynamically Biased Op Amp 2 A=2 A = 1.5 IOUT 1 I10 A=1 A = 0.3 A=0 0 0 1 vIN/ nVt 2 Allen and Holberg - CMOS Analog Circuit Design IX.7 - DYNAMICALLY BIASED AMPLIFIERS Dynamic circuits take advantage of the fact that many applications are synchronously clocked resulting in periods of time where the circuits is not functioning. Will examine: - Dynamic or switched resistors - Dynamically biased amplifiers - Dynamically biased, push-pull, cascode op amp Two Phase Clock φ1 φ1 switches on φ1 switches off 0 1 2 3 4 5 t/T 1 2 3 4 5 t/T φ2 φ2 switches on φ2 switches off 0 A Switched Resistance Realization φ2 φ1 D Pretune circuit φ2 φ2 G CG VSS S Switched resistor RFET φ1 Allen and Holberg - CMOS Analog Circuit Design A Continuous Time Resistor Realization with Increased Signal Swing i +D VC G1 + D2 G2 VSS vDS S1 M2 VSS RFET + - S2 D1 M1 VC -S Implementation of the Continuous Time Switched Resistor Realization using Dynamic Techniques φ2 φ2 φ1 CG VSS M2 Pretune circuit RFET φ2 VSS φ2 CG M1 Switched resistor φ1 Allen and Holberg - CMOS Analog Circuit Design Dynamically Biased Inverter VDD CB M2 φ2 φ2 iD vOUT COS φ1 M1 + vIN - φ2 VSS During phase 2 the offset and bias of the inverter is sampled and applied to C OS and C B. During phase 1 COS is connected in series with the input and provides offset cancelling plus bias for M1. CB provides the bias for M2. Allen and Holberg - CMOS Analog Circuit Design Dynamic, Push-pull, Cascode Op Amp Simplified schematic - VDD M8 VDD + VB2 - φ1 φ2 M4 M7 M3 C2 φ2 IB VDD φ1 vIN vOUT v+ IN C1 VSS M2 M6 φ1 M5 φ2 M1 + VB1 - VSS VSS Allen and Holberg - CMOS Analog Circuit Design Dynamic, Push-pull, Cascode Op Amp - Cont'd Phase 1 Clock Period VDD M8 M7 VDD + - VDD - VB2 - v+ IN C2 v+ IN IB C1 v+ - VSS - VB1 IN VSS M6 M5 VSS Phase 2 Clock Period VDD M4 v- - v+ + VDD - VB2 IN IN M3 VDD + - C2 VDD - VB2 - v+ IN vIN v+ IN - VSS - VB1 vOUT C1 M2 v- - v+ + VSS + VB1 IN IN VSS M1 VSS Allen and Holberg - CMOS Analog Circuit Design A Dynamic Op Amp which Operates on Both Clock Phases VDD φ2 M8 φ1 φ1 M4 φ2 M7 VDD M3 C2 RB vIN φ2 φ1 φ2 C3 M2 M6 φ2 M5 vOUT v+ IN φ1 C1 VSS C4 φ1 VDD VSS φ1 M1 φ2 VSS 1.6 mW dissipation Settling time = 10 ns into 5 pF GB ≈ 130 MHz with CL = 2.2 pF 1.5 µm technology Used with a 28.6 MHz clock to realize a 5th order switched capacitor filter with a cutoff frequency of 3.5 MHz. Allen and Holberg - CMOS Analog Circuit Design Page X.0-1 X. CMOS DATA CONVERTERS Contents X.1 Characterization and definition of D/A converters X.2 Voltage scaling D/A converters X.3 Charge scaling D/A converters X.4 Voltage and charge scaling D/A converters X.5 Other types of D/A converters, X.6 Characterization and definition of A/D converters X.7 Serial A/D converters X.8 Medium-speed A/D converters X.9 High-speed A/D converters (Flash, two-step, multiple pipe) X.10 Oversampled A/D converters X.11 Examples of A/D converters, limits of A/D converters Organization Chapter 10 D/A and A/D Converters Chapter 11 Analog Systems SYSTEMS Chapter 7 CMOS Comparators Chapter 8 Simple CMOS OTA's Chapter 9 High Performance OTA's COMPLEX CIRCUITS Chapter 5 CMOS Subcircuits Chapter 6 CMOS Amplifiers SIMPLE Chapter 2 CMOS Technology DEVICES Chapter 3 CMOS Device Modeling Chapter 4 Device Characterization Allen and Holberg - CMOS Analog Circuit Design Page X.0-2 Importance of Data Converters in Signal Processing ANALOG SIGNAL (Speech, sensors, radar, etc.) DIGITAL PROCESSOR (Microprocessor) PRE-PROCESSING (Filtering and analog to digital conversion) POST-PROCESSING (Digital to analog conversion and filtering) CONTROL ANALOG A/D DIGITAL D/A ANALOG ANALOG OUTPUT SIGNAL Allen and Holberg - CMOS Analog Circuit Design Page X.0-3 A/D and D/A Converters in Data Systems Analog computer Audio signals Video signals Power sources Chemical cells Synchros/resolvers Pressure cells Thermocouples Strain gages Bridges Photomultiplier Etc. Multiplexer Sample and Hold Analog to Digital Converter Digital System Transmission links Magnetic tape recorders Computer memories Paper tape recorders Real-time processor Comparators System and process controls Numerical machine controls Minicomputers Miroprocessors Etc. Reference Transmission links Magnetic tape recorders Computer memories Paper tape recorders Real-time processor Comparators System and process controls Numerical machine controls Minicomputers Miroprocessors Etc. Digital System Digital to analog converter Reference Filter Amplifier Audio systems Controllers Actuators CRT displays Analog recorders Analog computers Hybrid computers Analog meters Transducers Servomotors X-Y plotters Modems Etc. Allen and Holberg - CMOS Analog Circuit Design Page X.1-1 X.1 - CHARACTERIZATION AND DEFINITION OF CONVERTERS General Concept of Digital-to-Analog (D/A) Converters Reference b0 b1 b2 b3 Digital-toAnalog Converter vOUT or iOUT bN-1 vOUT = KVrefD or iOUT = KIrefD where K = gain constant (independent of digital input) b1 b2 b N-1 b0 D = N + N-1 + N-2 + ···· + 1 = scaling factor 2 2 2 2 Vref (I ref ) = voltage (current) reference bN-1 = most significant bit (MSB) b0 = least significant bit (LSB) For example, b1 b2 bN - 1 b0 vOUT = KV ref N + N-1 + N-2 + · ··· + 2 2 2 21 N-1 1 b j2 j = KVref N 2 j=0 ∑ Allen and Holberg - CMOS Analog Circuit Design Page X.1-2 Basic Architecture of a D/A Converter Continuous Time D/A Converter- Voltage References Vref DVref Scaling Network vOUT = K DVref Output Amplifier Binary Switches b0 b1 b2 bN-1 Clocked D/A ConverterVref b0 b1 b2 Latch Digital V out to analog converter bN-1 Clock Sample and hold V* out Allen and Holberg - CMOS Analog Circuit Design Page X.1-3 Classification of D/A Converters Done by how the converter is scaledD/A Converters Serial Charge Parallel Voltage Charge Voltage and Charge Slow Fast Current Allen and Holberg - CMOS Analog Circuit Design Page X.1-4 Static Characterization of D/A Converters Ideal input-output D/A converter Static Characteristic 1.000 0.875 Analog Ouput Value 0.750 1 LSB 0.625 Ideal analog output 0.500 0.375 0.250 0.125 0.000 000 001 010 011 100 101 Digital Input Code An ideal LSB change causes an analog change of Vref 2N 110 111 Allen and Holberg - CMOS Analog Circuit Design Page X.1-5 Definitions Resolution is the smallest analog change resulting from a 1 LSB digital change (quantified in terms of N bits). Quantization Noise is the inherent uncertainty in digitizing an anlog value with a finite resolution converter. Infinite resolution analog output - finite resolution analog output 0.5LSB 0.5 VREF 2N = VREF 2 N+1 Digital Input Code -0.5LSB 000 -0.5 001 010 VREF 011 2N = -VREF 2 N+1 Dynamic range (DR) is the ratio of FS to the smallest resolvable difference. 2N − 1 V REF FS 2N DR = LSB change = = 2N − 1 1 VREF N 2 N − 1) ≅ 6N dB DR(dB) = 20 log 10( 2 Signal to noise ratio (SNR) for a sawtooth waveform Approximating FS = LSB(2N -1) ≅ LSB(2 N), 2N Full scale RMS value 12 N 22 SNR = RMS value of quantization noise = = 2 1 22 12 6 6 2 N = 20 log 10 + 20 log10 (2 N) 2 2 SNR (dB) = 20 log 10 = 20 log10(1.225) + 6.02N = 1.76 dB + 6.02N dB Allen and Holberg - CMOS Analog Circuit Design Page X.1-6 Definitions - Continued Full scale (FS) is the the maximum DAC analog output value. It is one LSB less than V REF . FS = VREF 2N − 1 2N A monotonic D/A (A/D) converter is one in which an increasing digital input code (analog input) produces a continuously increasing analog output value (digital output code). Offset error is a constant shift of the actual finite resolution characteristic from the ideal infinite resolution characteristic. Gain error is a deviation between the actual finite resolution characteristic and the ideal infinite resolution characteristic which changes with the input . Integral nonlinearity (INL) is the maximum difference between the actual finite resolution characteristic and the infinite resolution characteristic. Differential nonlinearity (DNL) is the maximum deviation of any analog FS output changes caused by an input LSB change from its ideal change of N 2 . Allen and Holberg - CMOS Analog Circuit Design Page X.1-7 3-BIT D/A CONVERTER ILLUSTRATION VREF Ideal D/A conversion Normalized analog output (Ratio to VREF) 7 8 3 4 1 LSB 5 8 1 2 Ideal analog output 3 8 1 4 1 8 0 000 0 001 010 011 100 101 110 111 1 8 2 8 3 8 4 8 5 8 6 8 7 8 Digital input, code and fractional value Ideal relationship 8 8 Allen and Holberg - CMOS Analog Circuit Design Page X.1-8 7 8 7 8 5 8 5 8 3 3 8 Gain Error Offset 8 Error 1 8 0 000 001 010 011 100 101 110 111 Offset Error 7 8 1 8 0 000 001 010 011 100 101 110 111 Gain Error 7 8 Nonlinearity 5 8 5 8 3 8 3 8 1 8 0 Nonmonotonicity 1 8 0 000 001 010 011 100 101 110 111 Linearity Error 000 001 010 011 100 101 110 111 Nonmonotonicity (Due to Excessive Differential Nonlinearity) Typical sources of errors Allen and Holberg - CMOS Analog Circuit Design Page X.1-9 Integral and Differential Linearity for a D/A Converter D/A Converter with ±1.5 LSB integral nonlinearity and ±0.5 LSB differential nonlinearity 10 0.5 LSB Analog output (Ideal LSB) 9 8 7 6 1.5 LSB 5 4 3 Ideal 2 1 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1011 Digital word output D/A converter with ±1 LSB integral nonlinearity and ±1 LSB differential nonlinearity Ideal 10 Analog output (Ideal LSB) 9 0 LSB 8 7 1 LSB 6 5 4 2 LSB 3 2 1 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1011 Digital word output Allen and Holberg - CMOS Analog Circuit Design Page X.2-1 X.2 VOLTAGE SCALING CONVERTERS 3-BIT VOLTAGE SCALING D/A CONVERTER Assume that b0 = 1, b1 = 0, and b2 = 1 MSB: b2 LSB: b0 +VREF b0 b0 b1 b1 b2 b2 R/2 8 R 7 R 6 R 5 R vOUT 4 R 3 R 2 R 1 R/2 vOUT = VREF V REF 11 ( D+0.5) = 16 ( 2D+1) = 0.6875VREF = 16 VREF 8 Allen and Holberg - CMOS Analog Circuit Design Page X.2-2 3-BIT VOLTAGE SCALING D/A CONVERTER - CONT'D Input-Output Characteristics: VREF 7VREF 8 OUT 6VREF 8 5VREF 8 4VREF 8 3VREF 8 2VREF 8 VREF 8 000 001 010 011 100 101 110 Advantages: Inherent monotonicity Compatible with CMOS technology Small area if n < 8 bits Disadvantages: Large area if n > 8 bits Requires a high input impedance buffer at output Integral linearity depends on the resistor ratios 111 Input Allen and Holberg - CMOS Analog Circuit Design Page X.2-3 3-BIT VOLTAGE SCALING D/A CONVERTER WHICH MINIMIZES THE SWITCHES Require time for the logic to perform b0 b1 b2 +VREF R/2 8 3-to-8 Decoder R 7 R 6 R 5 R 4 R 3 R 2 R 1 R/2 vOUT Allen and Holberg - CMOS Analog Circuit Design Page X.2-4 Accuracy Requirements of a Voltage Scaling D/A Find the accuracy requirements for the voltage scaling D/A converter as a function of the number of bits N if the resistor string is a 5 micron wide polysilicon strip. If the relative accuracy is 2%, what is the largest number of bits that can be resolved to within ±0.5 LSB? Assume that the ideal voltage to ground across k resistors is kR V k = N VREF 2R The worst case variation in Vk is found by assuming all resistors above this point in the string are maximum and below this are minimum. Therefore, V k' = kRminVREF ( 2N-k) R max + k R min The difference between the ideal and worst case voltages is, Vk Vk' kRmin kR -V =N- N VREF 2 R ( 2 -k) R max + k R min REF Assuming that this difference should be less than 0.5 LSB gives, kRmin kR 0 .5 -N <N 2NR ( 2 -k) R max + k R min 2 Expressing Rmax as R+0.5∆R and Rmin as R-0.5∆R and assuming the worst case occurs midway in the resistor string where k=0.5( 2N) and assuming that 5 micron polysilicon has a 2% relative accuracy gives, 0.5(R- 0.5 ∆ R) 1 ∆R 1 0 . 5 - 0.5(R + 0.5 ∆ R) + 0.5(R- 0.5 ∆ R) = 4 R < 2 2-N ⇒ ∆R 1 < N-1 R 2 or 0.25(0.02) < 0.5( 2-N) ⇒ N = 6 Allen and Holberg - CMOS Analog Circuit Design Page X.2-5 R-2R LADDER DAC's Configuration: R A 2R 2R R B 2R R 2R b1 b0 R C 2R b2 2R b N-1 bN + - Equivalent circuit at A: R A b0 VREF + 2 - Equivalent circuit at B: R + - b0 VREF 2 R R B 2R + b1 VREF - + ( b4 + b2 )V 0 = - B 1 REF Finally, the equivalent circuit at Q: + - ( b0 2N Q R b1 b2 b + N-1 + N-2 +...+ N-1 VREF 2 2 2 vOUT R - ) sign bit + R bN + VREF VREF Allen and Holberg - CMOS Analog Circuit Design Page X.3-1 X.3 CHARGE SCALING D/A CONVERTER Binary weighted capacitor array: C 2 C φ C 2N-2 C 4 C 2N-1 v OUT C 2 N-1 + 1 SN-1 φ 2 SN-2 φ 2 SN-3 S1 φ 2 φ S0 2 φ 2 Terminating capacitor VREF Operation: 1.) During φ1, all capacitors are discharged. 2.) During φ 2 , capacitors with bi = 1 are connected to VREF and capacitors with bi = 0 are grounded. 3.) The resulting output voltage is, bN-1C b N-2 C/2 b N-3 C/4 b 0 C / ( 2N-1) vOUT = VREF 2C + 2C + 2C + . .. + 2C If Ceq. is defined as the sum of all capacitances connected to VREF, then Ceq. vOUT = 2C VREF + Ceq. vOUT VREF - 2C-Ceq. Allen and Holberg - CMOS Analog Circuit Design Page X.3-2 Other Versions of the Charge Scaling D/A Converter Bipolar Operation: Charge all capacitors to V REF. If bi = 1, connect the capacitor to ground, if bi = 0, connect the capacitor to VREF. Will require an extra bit to decide whether to connect the capacitors initially to ground or to VREF. Four-Quadrant Operation: If VREF can have ±values, then a full, four quadrant DAC can be obtained. Multiplying DAC: If VREF is an analog signal (sampled and held), then the output is the product of a digital word and an analog signal and is called a multiplying DAC (MDAC). Allen and Holberg - CMOS Analog Circuit Design Page X.3-3 Influence of Capacitor Ratio Accurcy on No. of Bits Use the data of Fig.2.4-2 to estimate the number of bits possible for a charge scaling D/A converter assuming a worst case approach and the worst conditions occur at the midscale (1 = MSB). The ideal output of the charge scaling DA converter is, vOUT Ceq. VREF = 2C The worst case output of the charge scaling DA converter is, Ceq.(min) v'OUT VREF = 2C - C eq. ( max) + C eq. (min) The difference between the ideal output and the worst case output is, vOUT v 'O U T Ceq.(min) 1 -V = 2 - 2C - C VREF ( eq.) (max) ± C eq.(min) REF Assuming the worst case condition occurs at midscale, then Ceq. = C ∴ vOUT v 'O U T VREF - VREF C(min) 1 = 2-C (max) - C (min) If C(max) = C + 0.5∆C and C(min) = C - 0.5∆C, then setting the difference between the ideal and worst case to 0.5LSB gives, 0.5( C (max) ± C (min)) - C (min) ≤ 0.5( 1/2N) C (max) + C (min) or 1 C(max) - C (min) ≤ N ( C (max) + C (min)) 2 or ∆C ≤ 1 2C ⇒ 2N ∆C 2C ≤ 2-N ⇒ ∆C 1 ≤ N-1 C 2 A 50µm x 50µm unit capacitor gives a relative accuracy of 0.1% and N = 11 bits. It is more appropriate that the relative accuracy is a function of N. For example, if ∆C/C ≈ 0.001 + 0.0001N, then N=9 bits. Allen and Holberg - CMOS Analog Circuit Design Page X.3-4 Increasing the Number of Bits for a Charge Scaling D/A Converter Use a capacitive divider. For example, a 13-bit DACLSB Array MSB Array - 1.016pF (Attenuating capacitor) + 1pF 2pF 8pF 4pF 16pF 32pF 1pF 2pF 4pF 8pF 16pF 32pF v OUT 64pF 1pF b0 b1 b0 b2 b1 b3 b2 b4 b3 b5 b4 b6 b6 b5 b8 b7 b9 b7 b8 b 11 b 10 b9 b 10 b12 b 11 b 12 +VREF - VREF 5 VL =∑ i=0 12 ±bi Ci VREF i=6 ±b iCi VREF 64 127 VR = ∑ An equivalent circuit1 64 1 + C = 1 ⇒ C = 63 ≈ 1.016 64 + 1.016pF 64pF vOUT 127pF + + VR VL - - 1 1 27 = 128 V R + 128 VL - ∑ 12 VR = ±biVREFCi 127 ∑ 5 and VL= i=6 or 63 1 1 + 64 64 127 =1 VR + 1 63 1 63 1 VL + 64 + 127 + 64 + 127 64 64 12 ±VREF ∑ vOUT = 128 i=6 b iC i ±biVREFCi 64 i=0 biCi + ∑ 64 5 i=0 Allen and Holberg - CMOS Analog Circuit Design Page X.3-5 Removal of the Amplifier Input Capacitance Effects Use the binary weighted capacitors as the input to a charge amplifier. Example of A Two-Stage Configuration: VREF φ bb 100 φ bb φ bb φ bb φ bb φbb 111 122 133 1 155 44 φb b 166 φbb 177 C 8 C 4 C 2 C 4 C 2 C 8 C C 8 φ 1 2C + v OUT C Allen and Holberg - CMOS Analog Circuit Design Page X.4-1 X.4 - VOLTAGE SCALING-CHARGE SCALING DAC'S VREF R(2M-1) SF v OUT R(2M-2) Ck-1 2k-1 C R(2M-3) C k-2 k-2 2 C1 2C C0 C C C M=4 k=8 SA R1 A S(k-1)A SB S(k-2) A S1A S0A S(k-1)B S(k-2) B S1B S0B R0 B Advantages: • Resistor string is inherently monotonic so the first M bits are monotonic. • Can remove voltage threshold offsets. • Switching both busses A and B removes switch imperfections. • Can make tradeoffs in performance between the resistors and capacitors. • Example with 4 MSB's voltage scaling and 8 LSB's charge scaling: Allen and Holberg - CMOS Analog Circuit Design Page X.4-2 Voltage Scaling, Charge Scaling DAC - Cont'd Operation: 1.) SF, SB, and S1B through Sk,B are closed discharging all capacitors. If the output of the DAC is applied to any circuit having a nonzero threshold, switch SB could be connected to this circuit to cancel this threshold effect. 2.) Switch SF is opened and buses A and B are connected across the resistor whose lower and upper voltage is V'REF and V'REF + 2-MVREF respectively, where b1 b2 bM - 1 b0 V'REF = V ref M + M-1 + M-2 + · ··· + 2 2 2 21 + 2k-1 C REF 2C C C vOUT A + 2-MV 2k-2 C S k,A - B S k-1,A S 2A SA S k,B S k-1,B S 2B SB - + V 'REF - 3.) Final step is to determine whether to connect the bottom plates of the capacitors to bus A (bi=1) or bus B (bi=0). Ceq. 2-MVREF - 2KC - Ceq. vOUT - + V 'REF - M+K-1 + + vOUT = ∑bi2-(M+K-i) VREF i=0 Allen and Holberg - CMOS Analog Circuit Design Page X.4-3 Charge Scaling, Voltage Scaling DAC Use capacitors for MSB's and resistors for LSB's vOUT 2N-1C 2 N-2C 2 N-3C VREF 4C 2C C C R VREF Switch network MSBs R R LSBs R R • Resistors must be trimmed for absolute accuracy. • LSB's are monotonic. Allen and Holberg - CMOS Analog Circuit Design Page X.5-1 X.5- OTHER TYPES OF D/A CONVERTERS CHARGE REDISTRIBUTION SERIAL DAC Precharge to VREF if bi = "1" Redistribution switch S1 S4 S2 VREF S3 + VC1 - C1 Precharge C1 to ground if bi = "0" C2 + VC2 - Initially discharge S4 C1 = C2 b0 = LSB b1 = NLSB . . . bN = MSB Conversion sequence: 4 Bit D/A Converter INPUT WORD: 1101 1 13/16 3/4 VC1 /VREF 1/2 1/4 0 2 4 6 8 1 13/16 3/4 VC2 /VREF 1/2 1/4 0 2 4 6 8 Close S4: VC2 = 0 Start with LSB firstClose S2 (b0=1): VC1 = VREF VREF Close S1: VC1 = 2 = VC2 Close S3 (b1=0): VC1 = 0 VREF Close S1: VC1 = VC2 = 4 Close S2 (b2=1): VC1 = VREF 5 Close S1: VC1 = VC2 = 8 VREF Close S2 (b3=1): VC1 = VREF 13 Close S1: VC1 = VC2 = 16 VREF Comments: • LSB must go first. • n cycles to make an n-bit D-A conversion. • Top plate parasitics add error. • Switch parasitics add error. Allen and Holberg - CMOS Analog Circuit Design Page X.5-2 ALGORITHMIC SERIAL DAC Pipeline Approach to Implementing a DAC: 1/2 1/2 ∑ 0 1/2 1/2 ∑ -1 z b0 ∑ -1 z b1 LSB bN-1 MSB VREF bN-2 b0 bN-1 vOUT (z) = 2 z-1 + 4 z -2 + .... + N z-N VREF 2 where bi = 1 or 0 Approaches: 1.) Pipeline with N cascaded stages. 2.) Algorithmic. vOUT(z) = bi z-1VREF 1 - 0.5z - 1 z -1 vOUT Allen and Holberg - CMOS Analog Circuit Design Page X.5-3 Example of an Algorithmic DAC Operation Realization using iterative techniques: A +VREF (Bit "1") B 0 + ∑ + Sample and hold VOUT (Bit "0") 1 2 Assume that the digital word is 11001 in the order of MSB to LSB. The steps in the conversion are: 1.) VOUT(0) is zeroed. 2.) LSB = 1, switch A closed, VOUT (1) = VREF . 3.) Next LSB = 0, switch B closed, VOUT(2) = 0 + 0.5VREF VOUT (2) = 0.5V REF . 4.) Next LSB = 0, switch B closed, VOUT (3) = 0 + 0.25VREF VOUT (3) = 0.25VREF. 5.) Next LSB = 1, switch A closed, VOUT(4) = VREF + (1/8)VREF VOUT(4) = (9/8)VREF . 6.) Finally, the MSB is 1, switch A is closed, and VOUT(5) = VREF + (9/16)VREF VOUT(5) = (25/16)VREF 7.) Finally, the MSB+1 is 0 (always last cycle), switch A is closed, and VOUT(6) = (25/32)VREF Allen and Holberg - CMOS Analog Circuit Design Page X.6-1 X.6 - CHARACTERIZATION OF ANALOG TO DIGITAL CONVERTERS General A/D Converter Block Diagram Digital Processor x(t) Filtering Sampling A/D Converter Types 1.) Serial. 2.) Medium speed. 3.) High speed and high performance. 4.) New converters and techniques. Quantization Digital Coding y(kTN) Allen and Holberg - CMOS Analog Circuit Design Page X.6-2 Characterization of A/D Converters Ideal Input-Output Characteristics for a 3-bit ADC 111 Ideal A/D conversion Output digital number 110 Normal quantized value (± 1/2 LSB) 101 100 Ideal transition 011 010 Ideally quantized analog input 1 LSB 001 0 000 1 8 1 FS 8 2 8 3 8 4 8 5 8 6 8 7 8 2 FS 3 FS 4 FS 5 FS 6 FS 7 FS 8 8 8 8 8 8 Normal quantized value (± LSB) FS Allen and Holberg - CMOS Analog Circuit Design Page X.6-3 Nonideal Characteristics of A/D Converters Offset error 111 111 110 Ideal Digital output code Digital output code 110 101 100 011 Gain error 101 100 011 010 010 001 Ideal 001 000 1 FS 4 1 FS 2 3 FS 4 000 FS 1 FS 4 1 FS 2 3 FS 4 Analog input value Analog input value Offset Error FS Scale factor (gain) error 111 111 110 110 Digital output code Digital output code Ideal 101 100 Ideal 011 Nonlinearity 010 100 Missed codes due to excessive differential nonlinearity 011 010 001 000 101 001 1 FS 4 1 FS 2 3 FS 4 Analog input value Integral Nonlinearity 000 FS 1 FS 4 1 FS 2 3 FS 4 Analog input value Differential Nonlinearity FS Allen and Holberg - CMOS Analog Circuit Design Page X.6-4 Sampled Data Aspect of ADC's S-H command Sample Hold Hold Amplitude ta ts Output valid for A/D conversion S* S(t) S* S(t) t Tsample = ts + ta ta = acquisition time ts = settling time tADC = time for ADC to convert analog input to digital word. Conversion time = ts + ta + tADC. kT Noise = C V 2 (rms) Allen and Holberg - CMOS Analog Circuit Design Page X.6-5 Sample and Hold Circuits Simple - φ vO A1 + vI CH Improved φ φ - φ - vO A2 + A1 + vI CH Waveforms v0(t) Volts v1(t), v0(t) v1(t) Switch closed (sample) Switch open (hold) Switch closed (sample) t Allen and Holberg - CMOS Analog Circuit Design Page X.7-1 X.7 - SERIAL A/D CONVERTERS Single-Slope, A/D Converter vIN* NT NT + Ramp generator VREF vr Output counter - vr vIN* Reset Output 0 NT t Interval counter f= 1 T clock • Simplicity of operation • Subject to error in the ramp generator • Long conversion times Allen and Holberg - CMOS Analog Circuit Design Page X.7-2 Dual Slope, A/D Converter Block Diagram: 1 Vin* 2 Positive integrator -VREF vint Vth + - Digital control Counter Binary output Operation: 1.) Initially vint = 0 and vin is sampled and held (Vin* > 0). 2.) Reset by integrating until vint(0) = Vth. 3.) Integrate Vin* for Nref clock cycles to get, NrefT * ⌠* vint(t1) = vint (NrefT) = k ⌡Vin dt + vint(0) = kNrefTVin + Vth 0 * 4.) The Carry Output on the counter is used to switch the integrator from Vin to -V REF. Integrate until vint is equal to Vth resulting in NoutT + t1 ⌠-VREFdt = V th vint(t1 + t2) = vint(t1) + k ⌡ t1 Nout * * = V in ∴ kNref TVin + Vth - kVREFNoutT= Vth ⇒ VREF N ref Allen and Holberg - CMOS Analog Circuit Design Page X.7-3 Waveform of the Dual -Slope A/D Converter vin V''' in V'' in V'in Vth 0 t 0 t1 = NrefT Reset t0 (start) t'2 t'' 2 t''' 2 t2 = Nout T • Very accurate method of A/D conversion. • Requires a long time -2( 2N) T Allen and Holberg - CMOS Analog Circuit Design Page X.7-4 Switched Capacitor Integrators Noninverting: C1 + v1 (t) C2 φ1 φ2 φ2 φ1 + + v2 (t) fsignal << fclock - - Operation: Assume non-overlapping clocks φ1 and φ2. During φ1, C1 is charged to v1[ ( n-1) T] giving a charge of q1[ ( n-1) T] on C1. During φ2, the charge across C1 is added to the charge already on C2 which is q2[ ( n-1) T] resulting in a new charge across C2 designated as q2( nT) . The charge equation can be written as, q2( nT) = q2[ ( n-1) T] + q1[ ( n-1) T] or C2v2( nT) = C2 v2 [ ( n-1) T] + C1 v1 [ ( n-1) T] Using z-domain notation gives C2v2(z) = C2z-1v2(z) + C1z-1v1(z) or v2(z) C1 z-1 H(z) = v (z) = C2 1 - z-1 1 Allen and Holberg - CMOS Analog Circuit Design Page X.7-5 Replacing z by ejωT gives, T e-jωT C1 e-jω2 C jωT) = 1 = H(e C2 1 - e-jωT C2 jωT -jωT e 2 - e 2 ωo ( ωΤ/2) jω sin( ωΤ/2) exp( -jωΤ/2) Mag. error = Phase error where ωο = C1/( TC2) , sinx = ejx - e-jx 2j ≈ ωo jω 1 if f << fc = T Allen and Holberg - CMOS Analog Circuit Design Page X.7-6 Magnitude Plots of the Switched Capacitor Integrator ωo = ωc 2π ωT 2πf πf πω = 2f = f = 2 c c ωc Log Plot10 ωT ωo 2 ω sin ωT 2 H(ej ωt ) dB 0 ωo =0.5 ωc ωo ω -10 0.1 π ω πω 2 1 3 45 c Linear Plot10 8 6 ωT ωo 2 ω sin ωT 2 H(ej ωt ) 4 ωo ω 2 π 0 0 0.5 1 1.5 2 ω πω c 2.5 3 3.5 Allen and Holberg - CMOS Analog Circuit Design Page X.7-7 Switched Capacitor Integrators - Cont'd Inverting: C1 C2 φ2 + φ2 φ1 v1 (t) φ1 + + - v2 (t) - By a similar analysis, one can show that H(e jω T )≈- ωo jω , if f << fc = 1/T Settling Time and Slew Rate of the Op Amp Important when the op amp plus feedback circuit has two or more poles or the op amp has a second pole. φ1 t φ2 vout t Slew Rate Settling Time t Allen and Holberg - CMOS Analog Circuit Design Page X.8-1 X.8 - MEDIUM SPEED A/D CONVERTERS Conversion Time ≈ NT Successive ApproximationArchitecture: Conditional gate Input Comparator Output register D/A Converter Shift register Reference Clock Output End of conversion Start Successive Approximation Process: vo VREF 0.5 VREF 0 1 2 3 4 5 6 t T Allen and Holberg - CMOS Analog Circuit Design Page X.8-2 A Voltage-Charge Scaling Successive Approximation ADC Vref SF R1 R2 _ R3 2K-1C 2C C + A B SA SB R 2 M-1 C R2 M Capacitor switches V* in Resistor switches Clock Successive approx. register and switch control logic (M + K) bit output of A/D start Operation: 1.) With SF closed, the bottom plates of all capacitors are connected through switch SB to Vin*. (Automatically accounts for voltage offsets). 2.) After SF is opened, a successive approximation search among the resistor string taps to find the resistor segment in which the stored sample lies. 3.) Buses A and B are then connected across this segment and the capacitor bottom plates are switched in a successive approximation sequence until the comparator input voltage converges back to the threshold voltage. Capable of 12-bit monotonic conversion with a DL of ±0.5LSB within 50µs. Allen and Holberg - CMOS Analog Circuit Design Page X.8-3 A Successive Approximation ADC using a Serial DAC V* in + Data storage register - S2 precharge Vref Serial D/A converter (Fig. 10.3-1) Start S3 discharge S1 charge share S4 reset D/A control register Sequence and control logic Clock Shift left Parallel data transfer Shift right Conversion Sequence: 1.) Assume first K MSB's have been decided so that, 1 1 1 Digital word = aM N + aN-1 + ... + a N-K+1 N-K+1 + . 2 2N-1 2 2.) Assume (K + 1)th MSB is 1 and compare this analog output with Vin* to determine aN-K. 3.) Store aN-K in the DATA storage register and contiune. Allen and Holberg - CMOS Analog Circuit Design Page X.8-4 CHARGE REDISTRIBUTION SERIAL DAC Precharge to VREF if bi = "1" Redistribution switch S1 S4 S2 VREF S3 + VC1 - C1 Precharge C1 to ground if bi = "0" C2 + VC2 - Initially discharge S4 C1 = C2 b0 = LSB b1 = NLSB . . . bN = MSB Conversion sequence: 4 Bit D/A Converter INPUT WORD: 1101 1 13/16 3/4 VC1 /VREF 1/2 1/4 0 2 4 6 8 1 13/16 3/4 VC2 /VREF 1/2 1/4 0 2 4 6 8 Close S4: VC2 = 0 Store with LSB firstClose S2 (b0=1): VC1 = VREF VREF Close S1: VC1 = 2 = VC2 Close S3 (b1=0): VC1 = 0 VREF Close S1: VC1 = VC2 = 4 Close S2 (b2=1): VC1 = VREF 5 Close S1: VC1 = V C2 = 8 VREF Close S2 (b3=1): VC1 = VREF 13 Close S1: VC1 = V C2 = 16 VREF Comments: • LSB must go first. • n cycles to make an n-bit D-A conversion. • Top plate parasitics add error. • Switch parasitics add error. Allen and Holberg - CMOS Analog Circuit Design Page X.8-5 Serial ADC Waveform for an Input of (13/16Vref) 1 3 4 1 2 vc1 /Vref 1 4 01201 1 bit 234 01 2 bits 234 560 1 3 bits 234 5678 t/T 4 bits 1 3 4 1 2 vc2 /Vref 1 4 01201 2340 1 234 5601 23456 78 t/T Allen and Holberg - CMOS Analog Circuit Design Page X.8-6 A 1-BIT/PIPE PIPELINE A/D CONVERTER Single Bit/Stage, N-Stage Pipeline Converter • Converter in 1 clock cycle using storage registers • Requires N comparators • Dependent upon passive component linearity • Can use error correcting algorithms and self-calibration techniques Block Diagram of the 1-Bit/Pipe A/D Architecture MSB bi LSB +- +- +- 2 V* in ∑ ±1 vi-1 2 z-1 ±1 Vref ith stage Vi = 2Vi-1 - biVref ∑ bi = +1 if Vi-1 > 0 where b = -1 if V < 0 i i-1 Output of the n-th stage can be written as: N-1 N AiVin - ∑ ∏Aj bi + bN Vref VN = ∏ i=1 i=1 j=i+1 N where Ai and bi are the gain and bit value of the ith stage vi z-1 Allen and Holberg - CMOS Analog Circuit Design Page X.8-7 Graphical Examples illustrating operation Example 1 x2 -VREF 1 3/4 1 3/4 1 3/4 1/2 1/4 1/2 1/4 1/2 1/4 0 0 0 0 -1/4 -1/2 -1/4 -1/2 -1/4 -1/2 -1/4 -1/2 -3/4 -1 -3/4 -1 -3/4 -1 -3/4 -1 B=1 B=1 x2 -VREF 1 3/4 1/2 1/4 x2 B=0 +VREF B=1 Example 2 1 1 1 3/4 1/2 3/4 1/2 3/4 1/2 1/4 0 1/4 0 -1/4 -1/2 -3/4 -VREF x2 -VREF 1 3/4 1/2 1/4 0 -1/4 -1/4 -1/4 -1/2 -3/4 -1 1/4 0 -1/2 -3/4 -1/2 -3/4 x2 -1 B=0 -1 B=1 x2 +VREF -1 B=0 B=1 Allen and Holberg - CMOS Analog Circuit Design Page X.8-8 IDEAL STAGE PERFORMANCE Vi Vi-1 ith Stage Plot of: V = 2 V − bi ref ref Vi Vref 1 bi+1 =+1 -1 -.5 .5 0 1 bi+1 =-1 -1 bi =-1 bi , bi+1 [00] bi =+1 [01] [10] [11] 1.) bi+1 must change at 0, and ±0.5Vref. (when Vi-1=0 and ±0.5Vre f) 2.) bi must change at Vi=0. 3.) Vi cannot exceed Vref. 4.) Vi should not be less than Vref when Vi-1=±Vref. Vi-1 Vref Allen and Holberg - CMOS Analog Circuit Design Page X.8-9 IDEAL PERFORMANCE Example Assume V in* = 0.4V and Vref = 1V Input to the ith stage, Vi-1 Stage i Vi-1 > 0? Bit i 1 0.4 Yes 1 2 2(0.4000)-1 = -0.200 No 0 3 2(-0.200)+1 = +0.600 Yes 1 4 2(+0.600)-1 = +0.200 Yes 1 Results for various values ov Vin. Vin b(i) v(i+1) b(i+1) v(i+2) b(i+2) v(i+3) b(i+3) v(i+4) b(i+4) v(i+5) -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 1 1 1 1 1 1 1 1 1 1 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -1 -1 -1 -1 -1 1 1 1 1 1 -1 -1 -1 -1 -1 1 1 1 1 1 1 -1 -0.6 -0.2 0.2 0.6 -1 -0.6 -0.2 0.2 0.6 -1 -0.6 -0.2 0.2 0.6 -1 -0.6 -0.2 0.2 0.6 1 -1 -1 -1 1 1 -1 -1 -1 1 1 -1 -1 -1 1 1 -1 -1 -1 1 1 1 -1 -0.2 0.6 -0.6 0.2 -1 -0.2 0.6 -0.6 0.2 -1 -0.2 0.6 -0.6 0.2 -1 -0.2 0.6 -0.6 0.2 1 -1 -1 1 -1 1 -1 -1 1 -1 1 -1 -1 1 -1 1 -1 -1 1 -1 1 1 -1 0.6 0.2 -0.2 -0.6 -1 0.6 0.2 -0.2 -0.6 -1 0.6 0.2 -0.2 -0.6 -1 0.6 0.2 -0.2 -0.6 1 -1 1 1 -1 -1 -1 1 1 -1 -1 -1 1 1 -1 -1 -1 1 1 -1 -1 1 -1 0.2 -0.6 0.6 -0.2 -1 0.2 -0.6 0.6 -0.2 -1 0.2 -0.6 0.6 -0.2 -1 0.2 -0.6 0.6 -0.2 1 Allen and Holberg - CMOS Analog Circuit Design Page X.8-10 Output Voltage for a 4-stage Converter 1 0.8 Inputs (Volts) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 VIN (Volts) 0.4 0.6 0.8 1 Allen and Holberg - CMOS Analog Circuit Design Page X.8-11 RESOLUTION LIMITS OF THE 1-BIT/STAGE PIPELINE ADC 1st-Order Errors of The 1-Bit/Stage Pipeline ADC • Gain magnitude and gain matching (k1) • Offset of the X2 amplifier and the sample/hold (k2) • Comparator offset (k3) • Summer magnitude and gain matching (k4) • Summer offset (k 5) Illustration: + - ± k3 Vi-1 2 ± k2 + +∑ + bi Vref + ∑ ± k1 +∑ + ± k4 Vi = AiVi-1 + VOSi - biAsiVref where +1 if Vi-1 > ±k3 = ±VOCi bi = -1 if V < ±k = ±V i-1 3 OCi Ai = all gain related errors of the ith stage VOSi = system offset errors of the ith stage VOCi = the comparator offset of the ith stage Asi = the gain of the summing junction of the ith stage + ± k5 + ∑ Vi Allen and Holberg - CMOS Analog Circuit Design Page X.8-12 Generalization of the First-Order Errors Extending the ith stage first-order errors to N stages gives: N-1 N AiVin + ∑ ∏Aj VOSi + VOSN ∏ i=1 i=1 j=i+1 N VN = N-1 N - Vref ∑ ∏Aj Asibi + A sNbN i=1 j=i+1 Assuming identical errors in each stage gives: VN = A NVin + N ∑( AN-i) VOS i=1 N N-i - V ref∑( A ) Asbi i=1 Assuming only the first stage has errors: N VN = A12N-1Vin + 2N-1VOS1 - Vref2N-1As1b1 - Vref ∑( 2N-i) bi i=2 Allen and Holberg - CMOS Analog Circuit Design Page X.8-13 Identification of Errors 1. Gain Errors 2N( ∆A/A) < 1 ⇒ N=10 ⇒ ∆A 1 < 1000 A Illustration of gain errors Vi Vref 2∆A A 2∆A 1A 1+ 1 bi+1 =+1 -1 0 1 bi+1 =-1 -1 bi =-1 bi =+1 Vi-1 Vref Allen and Holberg - CMOS Analog Circuit Design Page X.8-14 Identification of Errors - Cont'd 2. System Offset Errors VOS < Vref 2N For N=10 and V ref = 1V, VOS < 1mV Illustration of system offset error Vi Vref 1+VOS 1 1+VOS bi+1 =+1 -1 0 1 bi+1 =-1 -1 bi =-1 bi =+1 Vi-1 Vref Allen and Holberg - CMOS Analog Circuit Design Page X.8-15 Identification of Errors - Cont'd 3. Summing Gain Error ∆As 1 < A s 2N ∆A 1 For N=10, A < 1024 Vi Vref 1+∆As /As 1-∆As /As -1 -0.5 0.5 1 Vi-1 Vref -1+∆As /As -1-∆As /As Allen and Holberg - CMOS Analog Circuit Design Page X.8-16 Identification of Errors - Cont'd 4. Comparator Offset Error The comparator offset error is any nonzero value of the input to a stage where the stage bit is caused to change. It can be expressed as: Vi = 2Vi-1 - biVref where +1 if Vi-1 > VOCi bi = -1 if V < V i-1 OCi Illustration of comparator offset error: Vi Vref bi+1 =+1 -1 -1 -0.5 0.5 bi+1 =-1 bi =-1 bi =+1 VOC = ? 1 Vi-1 Vref Allen and Holberg - CMOS Analog Circuit Design Page X.8-17 SUMMARY 1.) The 1-bit/pipe, pipeline converter which uses standard components including a sample and hold, an amplifier, and a comparator would be capable of realizing at most an 8 or 9 bit converter. 2.) The accuracy of the gains and offset of the first stage of an N-Bit converter must be within 0.5LSB. 3.) The accuracy of the gains and offset of a stage diminishes with the remaining number of stages to the output of the converter. 4.) Error correction and self-calibrating techniques are necessary in order to realize the potential resolution capability of the 1-bit/'stage pipeline ADC. Allen and Holberg - CMOS Analog Circuit Design Page X.8-18 Cyclic Algorithmic A/D Converter The output of the ith stage of a pipeline A/D converter is Voi = (2Vo,i-1 - biVREF )z-1 If Voi is stored and feedback to the input, the same stage can be used for the conversion. The configuration is as follows: Comparator Voi X2 +1 Sample and hold ∑ +Vref +1 -Vref Practical implementation: Comparator Va X2 +Vref Sample and hold Vb S1 Vin +1 ∑ -1 + - Vo Vo = "1" +Vref Vo = "0" Allen and Holberg - CMOS Analog Circuit Design Page X.8-19 Algorithmic ADC - Example Assume that Vin* = 0.8VREF. The conversion proceeds as; 1.) 0.8VREF is sampled and applied to the X2 amplifier by S1. 2.) Va(0) is 1.6VREF (b1=1) which causes -VREF to be subtracted from Va(0) giving Vb(0) = 0.6V REF 3.) In the next cycle, Va(1) is 1.2VREF (b2=1) and Vb(1) is 0.2VREF. 4.) The next cycle gives Va(2) = 0.4VREF (b3=0) and Vb(2) is 0.4VREF. 5.) The next cycle gives Va(3) = 0.8VREF (b4=0) and Vb(3) is 0.8VREF. 6.) Finally, V a(4) = 1.6V REF (b5=1) and V b(4) = 0.6V REF. ∴ The digital word is 11001. ⇒ Vanalog = 0.78125VREF. Va/VREF Vb /VREF 2.0 2.0 1.6 1.6 1.2 1.2 0.8 0.8 0.6 0.4 0.4 0.2 0 0 1 2 3 4 5 t T 1 2 3 4 5 t T Allen and Holberg - CMOS Analog Circuit Design Algorithmic A/D Converters-Practical Results • Only one accurate gain-of-two amplifier required. • Small area requirements • Slow conversion time - nT. • Errors: Finite op amp gain, input offset voltage, charge injection, capacitance voltage dependence. Practical Converter 12 Bits Differential linearity of 0.019% (0.8LSB) Integral linearity of 0.034% (1.5LSB) Sample rate of 4KHz. Page X.8-20 Allen and Holberg - CMOS Analog Circuit Design Page X.8-21 SELF-CALIBRATING ADC's S1 MAINDAC COMP CN CN-1 C1B C1A CCAL TO SUCCESIVE APPROXIMATION REGISTER Vref GND REGISTER CALIBRATION DAC SUBDAC SUCCESSIVE APPROXIMATION REGISTER ADDER DATA REGISTER CONTROL LOGIC VεN VεN-1 DATA OUTPUT Main ADC is an N-bit charge scaling array. Sub DAC is an M-bit voltage scaling array. Calibration DAC is an M+2 bit voltage scaling array. This is an voltage-scaling, charge-scaling A/D converter with (N+M)- bits resolution. Allen and Holberg - CMOS Analog Circuit Design Page X.8-22 Self-Calibration Procedure During calibration cycles, the nonlinearity factors caused by capacitor mismatching are calibrated and stored in the data register for use in the following normal conversion cycles. The calibration procedure begins from MSB by connecting CN to VREF and the remaining capacitors CNX to GND, then exchange the voltage connection as follows: VX CN VX CNX CN VREF CNX VREF where C NX = C1B + C1A + ... + C N-1 The final voltage VX after exchanging the voltage connections is VX = VREF CNX - CN CNX + C N If the capacitor ratio is accurate and CNX = CN ⇒ VX = 0, otherwise VX ≠ 0. This residual voltage VX is digitized by the calibration DAC. Other less significant bits are calibrated in the same manner. After all bits are calibrated, the normal successive-approximation conversion cycles occurs. The calibrated data stored in the data register is converted to an analog signal by calibration DAC and is fed to the main DAC by CCAL to compensate the capacitor mismatching error. Allen and Holberg - CMOS Analog Circuit Design Self-Calibrating ADC Performance Supply voltage ± 5V Resolution of 16 bits Linearity of 16 bits Offset less than 0.25 LSB Conversion time for 0.5 LSB linearity: 12 µs for 12 Bits 80 µs for 16 Bits. RMS noise of 40 µV. Power dissipation of 20 mW (excludes logic) Area of 7.5 mm (excludes logic). Page X.8-23 Allen and Holberg - CMOS Analog Circuit Design X.9 - HIGH SPEED ADC's Conversion Time ≈ T (T = clock period) • Flash or parallel • Time interleaving • Pipeline - Multiple Bits • Pipeline - Single Bit Page X.9-1 Allen and Holberg - CMOS Analog Circuit Design Page X.9-2 FLASH A/D CONVERTER VREF V* = 0.7 VREF in R 7 VREF 8 + R 1 - 6 VREF 8 + - R 5 VREF 8 + R 0 - 4 VREF 8 + + R 0 - 2 VREF 8 + + R 0 - R 1 VREF 8 0 - R 3 VREF 8 1 - • Fast conversion time, one clock cycle • Requires 2N-1 comparators • Maximum practical bits is 6 or less • 6 bits at 10 MHz is practical 0 Digital decoding network Output digital word 101 Allen and Holberg - CMOS Analog Circuit Design Page X.9-3 Time-Interleaved A/D Converter Array Use medium speed, high bit converters in parallel. T1 S/H N-bit A/D T2 S/H Vin N-bit A/D . .. Digital word out TM S/H N-bit A/D A/D Converter No.1 A/D Converter No.2 A/D Converter No.M T1 T2 TM T1 + TC T2 + TC TM + TC t Allen and Holberg - CMOS Analog Circuit Design Page X.9-4 Relative Die Size vs. Number of Bits 320 160 Relative die size FLASH 80 5 Succ. Approx. Array (m- WAY) 4 40 3 m 20 10 4 5 6 7 # of bits 8 9 Allen and Holberg - CMOS Analog Circuit Design Page X.9-5 2M-BIT, PARALLEL-CASCADE ADC • Compromise between speed and area • 8-bit, 1M Hz. Gain = 2M + V* in ∑ V* in Vref Vref + + - - + + - - + - Digital decoding network + - + + - Digital decoding network D/A Converter 2M - 1 equal resistors and comparators M MSB's 2M - 1 equal resistors and comparators M LSB's Allen and Holberg - CMOS Analog Circuit Design Page X.9-6 Conversion of Digital back to Analog for Pipeline Architectures Use XOR gates to connect to the appropriate point in the resistor divider resulting in the analog output corresponding to the digital output. Vref Analog Out V* in 1 + 0 1 + 1 + 0 0 + 0 0 Allen and Holberg - CMOS Analog Circuit Design Page X.10-1 X.10 - OVERSAMPED (∆-∑) A/D CONVERTER NYQUIST VERSUS OVERSAMPLED A/D CONVERTERS Oversampling A/D converters use a sampling clock frequency(fS) much higher than the Nyquist rate(fN). Conventional Nyquist ADC Block Diagram: Digital Processor x(t) Filtering Sampling Oversampling ADC Block Diagram Filtering Sampling Digital Coding Modulator x(t) Quantization Decimation Filter Quantization Digital Coding y(kTN) The anti-aliasing filter at the input stage limits the bandwidth of the input signal and prevents the possible aliasing of the following sampling step. The modulator pushes the quantization noise to the higher frequency and leaves only a small fraction of noise energy in the signal band. A digital low pass filter cuts off the high frequency quantization noise. Therefore, the signal to noise ratio is increased. y(kTN) Allen and Holberg - CMOS Analog Circuit Design Page X.10-2 ANTI-ALIASING FILTER The anti-aliasing filter of an oversampling ADC requires less effort than that of a conventional ADC. The frequency response of the anti-aliasing filter for the conventional ADC is sharper than the oversampling ADC. Conventional ADC's Anti-Aliasing Filter fB f fN/2 fS=fN Oversampling ADC's Anti-Aliasing Filter fB f fN/2 fN fS/2 fS fB : Signal Bandwidth fN : Nyquist Frequency, fN = 2fB fS : Sampling Frequency and usually fS >> fN fS M : Oversampling ratio, M = f N So the analog anti-aliasing filter of an oversampling ADC is less expensive than the conventional ADC. If M is sufficiently large, the analog anti-aliasing filter is simply an RC filter. Allen and Holberg - CMOS Analog Circuit Design Page X.10-3 QUANTIZATION Conventional ADC's Quantization The resolution of conventional ADCs is determined by the relative accuracy of their analog components. For a higher resolution, self-calibration technique can be adopted to enhance the matching accuracy. Multilevel Quantizer: output (y) 5 3 ideal curve -6 -4 -2 1 -1 2 -3 4 6 input (x) y=Gx+e -5 e 1 x -1 The quantized signal y can be represented by y = Gx + e where, G = gain of ADC, normally = 1 e = quantization error Allen and Holberg - CMOS Analog Circuit Design Page X.10-4 Conventional ADC's Quantization - Cont'd The mean square value of quantization error, e, is ∆/2 1⌠ ∆2 e2rms = ∆ ⌡ e(x)2 dx = 12 -∆/2 where VREF ) 2N When a quantized signal is sampled at fS (= 1/τ), all of its noise power folds into the frequency band from 0 to fS/2. If the noise power is white, then the spectral density of the ∆ = the quantization level of an ADC (typically sampled noise is 2 E(f) = erms f S 1/2 = erms 2τ where τ = 1/fS and fS = sampling frequency The inband noise energy no is fB 2 2fB erms 2 2⌡ 2 no = ⌠ E2(f)df = e rms (2fBτ) = erms f = M S 0 erms no = M fS The oversampling ratio M = 2f B Therefore, each doubling of the sampling frequency decreases the in-band noise energy by 3 dB, and increases the resolution by 0.5 bit. This is not a very efficient method of reducing the inband noise. Allen and Holberg - CMOS Analog Circuit Design Page X.10-5 OVERSAMPLING ADC fS analog fB input ∑∆ MODULATOR fD LOW-PASS 2 fB FILTER digital PCM DECIMATOR Oversampling ADCs consist of a ∑∆ modulator, a decimator (down-sampler), and a digital low pass filter. ∑∆ modulator Also called the noise shaper because it can shape the quantization noise and push majority of the noise to high frequency band. It modulates the analog input signal to a simple digital code, normally is one bit, using a sampling rate much higher the Nyquist rate. Decimator Also called the down-sampler because it down samples the high frequency modulator output into a low frequency output. Low-pass filter Use digital low pass filter to cut off the high frequency quantization noise and preserve the input signal. Allen and Holberg - CMOS Analog Circuit Design Page X.10-6 Sigma-Delta (∑∆) Modulator First Order ∑∆ Modulator The open loop quantizer in a conventional ADC can be modified by adding a closed loop to become a ∑∆ modulator. fS x(t) + + Integrator yi A/D - D/A Modulator Output input signal Amplitude (V) modulator output 0 0.5 Time (ms) 1 Allen and Holberg - CMOS Analog Circuit Design Page X.10-7 First-Order ∑∆ Modulator gn + xn wn+1 Delay wn yn en Quantizer Accumulator yn = wn + en (1) wn+1 = gn + wn = xn - yn + wn = xn -(wn + en) + wn = xn - en (2) Therefore, wn = xn-1 - en-1, which when substituted into (1) gives yn = xn-1 + ( en - en-1) The output of ∑∆ modulator yn is the input signal delayed by one clock cycle xn-1, plus the quantization noise difference en - en-1. The modulation noise spectrum density of en - en-1 is signal baseband ωτ ωτ N(f) = E(f) 1 - z-1 = E(f) 1 - e-jωτ = 2E(f) sin 2 = 2e rms 2τ sin 2 Plot of Noise Spectrum 2 N(f)/E(f) 1.5 1 N(f) E(f) 0.5 0 0 fB Frequency fS 2 Allen and Holberg - CMOS Analog Circuit Design Page X.10-8 First Order ∑∆ Modulator-Cont’d The noise power in the signal band is fB fB ⌠ ωτ 2 2 2 no = ⌠ N(f) df = 2erms 2τ sin 2 df ⌡ ⌡ 0 0 fB 2⌠ 2 no = ⌡ 2erms 2τ (πfτ) df 0 ωτ 2πf πf where sin 2 = sin = sin ≈ πfτ 2fS f S if fS >> f Therefore, fB 2 ermsπ2(2τfB)3 2 ⌡2 2 no ≈ (2τ)3π2 erms ⌠f df = 3 0 where , fS >> fB Thus, no = erms π π 2fBτ 3/2 = erms M-3/2 3 3 Each doubling of the oversampling ratio reduces the modulation noise by 9 dB and increase the resolution by 1.5 bits. Allen and Holberg - CMOS Analog Circuit Design Page X.10-9 Oversampling Ratio Required for a First-Order ∆ Σ Modulator A block diagram for a first-order, sigma-delta modulator is shown in the z-domain. Find the magnitude of the output spectral noise with VIN(z) = 0 and determine the bandwidth of a 10-bit analog-to-digital ∆ = rms value of converter if the sampling frequency, fS, 12 quantization is 10 MHz. noise + Vin (z) + Vout (z) Solution + 1 Σ Σ 1 z-1 Vout(z) = e rms + z-1 [Vin(z) Vout(z)] or z-1 Vout(z) = z erms if Vin(z) = 0 → Vout(z) = (1-z-1)erms ωτ ωτ 2 |N(f)| = E(f) 1 - e-jωτ = 2E(f) sin 2 = 2 erms sin 2 fS The noise power is found as fB fB ⌠ 2 π fτ 2 2 2 ⌡ no(f) = ⌠|N(f)|2 df = 2 erms sin2 2 df fS ⌡ 0 0 2 πf τ Let sin 2 ≈ πfτ if fS >> fB. Therefore, fB 2 2 2 8π2 2 fB 3 ⌡ no(f) = 4 f erms (πτ)2 ⌠f2 df = 3 erms fS S 0 or 3/2 VREF fB 8 ≤ 10 no(f) = π·erms f 3 2 S Solving for fB/fS gives (using ∆ in erms term is equal to VREF) fB 12 3 1 2/3 = [0.659x10-3]2/3 = 0.007576 = fS 8 π 210 fB = 0.007576·10MHz = 75.76kHz. Allen and Holberg - CMOS Analog Circuit Design Page X.10-10 Decimator (down-sampling) The one-bit output from the ∑∆ modulator is at very high frequency, so we need a decimator (or down sampler) to reduce the frequency before going to the digital filter. fS analog fB input ∑∆ fD LOW-PASS FILTER MODULATOR Removes the modulation noise from modulator xn 2 fB digital PCM DECIMATOR Removes the out-of-band components of the signal to low-pass filter + yn REGISTER fS fS 1N yn = N ∑ xn , where N = = down-sampling ratio fD N=0 The transfer function of decimator is N-1 1 1 - z-N Y(z) 1 H(z) = X(z) = N ∑ z-i = N 1 - z-1 i=0 sinc(πfNτ) H(ejωτ) = sinc(πfτ) Allen and Holberg - CMOS Analog Circuit Design Page X.10-11 Frequency Spectrum of the Decimator sinc(πfNτ) H(ejωτ) = sinc(πfτ) 10 0 Quantization Noise Signal Bandwidth Magnitude (dB) -10 -20 -30 -40 -50 fD Frequency fS 2 fD = intermediate decimation frequency When the modulation noise is sampled at fD, its components in the vicinity of fD and the harmonics of fD fold into the signal band. Therefore, the zeros of the decimation filter must be placed at these frequencies. Allen and Holberg - CMOS Analog Circuit Design Page X.10-12 Digital Lowpass Filter fS analog fB input ∑∆ fD LOW-PASS FILTER MODULATOR FIR or IIR digital low pass filter 10 Magnitude (dB) -20 -50 -80 -110 2 fB digital PCM DECIMATOR 4000 Frequency (Hz) Allen and Holberg - CMOS Analog Circuit Design Page X.10-13 After Digital Low Pass Filtering 0 Magnitude (dB) signal -50 -150 -100 quantization noise 0 1000 Frequency (Hz) Bit resolution From the frequency response of above diagram, the signal-to-noise ratio (SNR) signal SNR = 10log 10 f (dB) B ∑ noise(f) f=0 and Bit resolution (B) ≈ SNR(db) 6dB Allen and Holberg - CMOS Analog Circuit Design Page X.10-14 digital PCM FILTER Frequency 2fB Frequency Frequency Time Time MODULATOR analog fB input ∑∆ fS DECIMATOR fD LOW-PASS System block in time domain and frequency domain Allen and Holberg - CMOS Analog Circuit Design Page X.10-15 Second-Order ∑∆ Modulator Second order ∑∆ modulator can be implemented by cascading two first order ∑∆ modulators. INTEGRATOR 2 INTEGRATOR 1 xn DELAY A/D +∑ +∑ +∑ +∑ + + DELAY D/A QUANTIZER yn = xn-1 + (en - 2en-1 + en-2) The output of a second order ∑∆ modualtor yn is the input signal delayed by one clock cycle xn-1, plus the quantization noise difference en - 2en-1 + en-2. The modulation noise spectrum density of en - 2en-1 + en-2 is ωτ 2 2 N(f) = E(f) 1 - z-1 = E(f) 1 - e-jωτ = 4E(f) sin2 2 Noise Spectrum signal baseband 4 N(f)/E(f) 3 2 2nd order N(f) first order N(f) E(f) 1 0 0 fB Frequency fS 2 yn Allen and Holberg - CMOS Analog Circuit Design Page X.10-16 Second-Order ∑∆ Modulator- Cond’d The noise power in the signal band is ∆ 2 π2 -5/2 ∆π π2 -5/2 no = e rms M = M = ( M) -5/2 , fs >> fo 12 5 5 2 15 Each doubling of the oversampling ratio reduces the modulation noise by 15 dB and increase the resolution by 2.5 bits. Higher-Order Σ −∆ Modulators Let L = the number of loops. The spectral density of the modulation can be written as ωτ L | NL(f)| = e rms 2τ 2sin 2 The rms noise in the signal band is given approximately by πL no ≈ erms (2fBτ) L+0.5 2L+1 This noise falls 3(2L+1) dB for every doubling of the sampling rate providing L+0.5 extra bits. Decimation Filter sinc(πfNτ) L+1 is close to being optimum for decimating the A filter function of sinc(πfτ) signal from an Lth-order ∆−Σ modulator. Stability For orders greater than 2, the loop can become unstable. Loop configuration must be used that provide stability for order greater than two. Allen and Holberg - CMOS Analog Circuit Design Page X.10-17 The modulation noise spectral density of a second-order, 1-bit ∆ Σ modulator is given as |N(f)| = 4∆ 12 ωt 2 sin2 4 fs where ∆ is the signal level out of the 1-bit quantizer and fs = (1/τ) = the sampling frequency and is 10MHz. Find the signal bandwidth, fB, in Hz if the modulator is to be used in an 18 bit oversampled ADC. Be sure to state any assumption you use in working this problem. Allen and Holberg - CMOS Analog Circuit Design Page X.10-18 Circuit Implementation of A Second Order ∑∆ Modulator V+ REF VREF S1 S2 C1 C2 C2 S3 S4 IN S1 - S2 C1 + S3 S4 +S1 C1 S2 S4 S3 + +S1 C2 - C1 S2 OUT S4 S3 C2 VREF V+ REF Fully differential, switched-capacitor integrators can reduce charge injection effect. Circuit Tolerance of a Second Order ∑∆ Modulator 1. 20% variation of C1/C2 has only a minor impact on performance. 2. The Op Amp gain should be comparable to the oversampling ratio. 3. The unity-gain bandwidth of Op Amp should be at least an order of magnitude greater than the sampling rate. Allen and Holberg - CMOS Analog Circuit Design SOURCES OF ERRORS IN Σ ∆ A/D CONVERTERS 1. Quantization in time and amplitude Jitter and hysteresis 2. Linear Errors Gain and delay 3. Nonlinear Errors Harmonic distortion Thermal noise Page X.10-19 Allen and Holberg - CMOS Analog Circuit Design Page X.10-20 Comparison of the Various Examples Discussed Type of Converter ResoluNo. of No. of Dependent tion Cycles/ Compar on Passive Components Conver- ators sion Speed INL/DNL (LSB's) Area Power (mW) Flash 1 2N-1 Yes Low High N/A Largest Largest Two-Step Flash 2 31 Yes 10 bits 5Ms/s ±3/±0.6 350 1 after initial delay 3 Yes 13 bits 250ks/s ±1.5/±0.5 54k mils2 3600 mils2 64 3 Yes 16 bits 24kHz 75.3k mils2 110 Pipeline Oversampling 91dB 15 Allen and Holberg - CMOS Analog Circuit Design Page X.11-1 X.11 -FUNDAMENTAL LIMITS OF SAMPLING A/D C ONVERTERS kT/C Noise Assume that the ON resistance of a switch is R and the sampling capacitor is C and that the time to charge the capacitor fully is 1 T = f ≈ 10RC c (1) Set the value of the LSB = Vref = 2N V ref equal to kT/C noise of the switch, 2N kT C (2) Solve for C of (1) and substitute into (2) to get Vref N 2 2 = 10kTRfc ⇒ 2N f c = Vref 10kRT (3) Taking the log of both sides of (3) gives N = -1.67 log(fc) + 3.3 log(Vref) - 1.67 log(10kRT) or N = 32.2 + 3.33 log(V ref ) - 1.67 log(Rf c ) (At room temperature) kT/C Noise Comparison of high-performance, monolithic A/D converters in terms of resolution versus sampling frequency with fundamental limits due to kT/C noise superimposed. Allen and Holberg - CMOS Analog Circuit Design Page X.11-2 Fundamental Limits of Sampling A/D Converters - Continued Maximum Sample Rate Assume that the maximum sample rate is determined by the time required for the amplifiers and/or sample-hold circuits to settle with the desired accuracy for high resolution. Further assume that the dynamics of these circuits can be modeled by a second-order system with a transfer function of ω n2 A(s) =2 A(0) s + 2 ζω n s + ω n 2 If ω n ≈ GB of the circuit and if the system is underdamped, then the step response is given as e-ζGBt vo(t) =1- sin 1- ζ 2 G B·t + φ A(0) 1-ζ2 This response looks like the following, 2 1.5 +ε 1 -ε 0.5 0 Settling Time 0 4 8 ωn t 12 16 20 If we define the error (±ε) in vo settling to A(0) as the multiplier of the sinusoid, then an expression for the settling time can be derived as e-ζGBt 1 1 2πζGB ⇒ fsample = = ts = 2πζGB ln ts 1 1 - ζ2 ln ε 1-ζ2 For reasonable values of ζ, fsample can be approximated as πGB G B f sample ≈ 10 = 3 Allen and Holberg - CMOS Analog Circuit Design Page X.11-3 Aperature Uncertainty (Jitter) A problem in all clocked or sampled A/D converters. vin Clock Analog In Analog-todigital converter Digital Out ∆V ∆T dvin ∆V = slope x ∆T = dt ∆ T Vref/2N ∆V ∆T = Aperature uncertainty = dV = dv /dt in in dt Assume that vin(t) = Vp sin ωt dvin dt = ω V p max ∆T = Therefore, ∆ T = Vref Vref 1 1 x ωV ≈ N =N 2N 2 ωVref 2 ω p 1 1 = 2πf2N πf2N+1 Suppose f = 100kHz and N = 8, ∆T = 1 = 6.22ns 200πKx29 6.22ns 622ppm Clock accuracy = 10,000ns = 0.06% = ? Slope = dvin dt t Allen and Holberg - CMOS Analog Circuit Design Page X.12-1 X.12 - SUMMARY OF A/D CONVERTERS Typical Performance Characteristics A/D Architecture Typical Performance Characteristics Serial 1 = 2N T fc 1-100 conversions/sec., 12-14 bit accuracy, requires no element-matching, a stable voltage reference is necessary Successive Approximation 1 fc ≈ NT 10,000-100,000 conversions/sec., 8-10 bits of untrimmed or uncalibrated accuracy, 12-14 bits of trimmed or calibrated accuracy High Speed 1 T < f < NT c 1 to 40 megaconversions/sec., 7-9 bits of accuracy, 10-12 bits of accuracy with error correction and other techniques Oversampling 8,000-600,000 conversions/sec., 12-16 bits accuracy, requires linear integrators but no precision passive components, minimizes noise and offsets 1 << T fc Conclusions • The best A/D converter depends upon the application • Both resolution and speed are ultimately limited by the accuracy of the process • High resolution A/D's will be more oriented toward "signal averaging" type converters, particularly with shorter channel lengths ...
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