HW1soln-2730-F08

HW1soln-2730-F08 - set-dominant gated SR latch in which the...

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EE 2730 — HW 1 solutions 1 EE 2730 — Homework 1 solutions Fall 2008 1. Brown and Vranesic, Problem 7.3 - Figure 7.5 shows a latch built with NOR gates. Draw a similar latch using NAND gates. Derive its characteristic table and show its timing diagram, given the R and S inputs shown in Figure 7.5(c). 2. Brown and Vranesic, Problem 7.7 - The gated SR-latch in Figure 7.6a has unpredictable behavior if the S and R inputs are both equal to 1 when the Clk changes to 0. One way to solve this problem is to create a
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Unformatted text preview: set-dominant gated SR latch in which the condition S = R = 1 causes the latch to be set to 1. Design a set-dominant gated SR latch and show the circuit. EE 2730 HW 1 solutions 2 3. Show how to build a D flip-flop using a T flip-flop and combinational logic. 4. Brown and Vranesic, Problem 7.13 - A universal shift register can shift in both the left-to-right and right-to-left directions, and it has parallel-load capability. Draw a circuit for such a shift register....
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This note was uploaded on 06/20/2011 for the course EE 2730 taught by Professor Desouza during the Spring '08 term at LSU.

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HW1soln-2730-F08 - set-dominant gated SR latch in which the...

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