HW2soln-2730-F08

# HW2soln-2730-F08 - EE 2730 HW 2 solutions 1 EE 2730...

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1 EE 2730 — Homework 2 solutions Fall 2008 1. Brown and Vranesic, Problem 7.10 - Write Verilog code that represents a T flip-flop with an asynchronous clear input. Use behavioral code, rather than structural code. module tFipFop (T, Clock, Resetn, Q); input T, Clock, Resetn; output reg Q; always @( negedge Resetn, posedge Clock) if (!Resetn) Q <= 0; else if (T) Q <= ~Q; endmodule 2. Brown and Vranesic, Problem 7.19 - Consider the circuit in ±igure P7.4. How does this circuit compare with the circuit in ±igure 7.17(a)? Can the circuits be used for the same purposes? If not, what is the key difference between them? Clock S Q Q Clk R S Q Q Clk R Q Q J K Figure P7.4 Figure 7.17(a) — JK flip-flop The circuit in ±igure P7.4 is a master-slave JK Fip-Fop. It suffers from a problem sometimes called ones-catching . Consider the situation where the Q output is low, Clock = 0, and J = K = 0 . Now let Clock remain stable at 0 while J changes from 0 to 1 and then

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## This note was uploaded on 06/20/2011 for the course EE 2730 taught by Professor Desouza during the Spring '08 term at LSU.

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HW2soln-2730-F08 - EE 2730 HW 2 solutions 1 EE 2730...

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