HW4soln-2730-F08

# HW4soln-2730-F08 - EE 2730 HW 4 solutions EE 2730 Homework...

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1 EE 2730 — Homework 4 solutions Fall 2008 1. Brown and Vranesic, Problem 8.4 - Write Verilog code for the FSM described in Problem 8.3. (Problem 8.3 was on Homework 3 — FSM to generate z = 1 when the previous four values of w were 1001 or 1111) This answer follows my solution to Problem 8.3 given in the Homework 3 solutions. module prob8 4 (Clock, Resetn, w, z); input Clock, Resetn, w; output reg z; reg [3:1] y, Y; parameter [3:1] A = 3’b000, B = 3’b001, C = 3’b010, D = 3’b011, E = 3’b100, F = 3’b101; // Define the next state and output combinational circuits always @(w, y) case (y) A: if (w) begin Y = B; z = 0; end else begin Y = A; z = 0; end B: if (w) begin Y = E; z = 0; end else begin Y = C; z = 0; end C: if (w) begin Y = B; z = 0; end else begin Y = D; z = 0; end D: if (w) begin Y = B; z = 1; end else begin Y = A; z = 0; end E: if (w) begin Y = F; z = 0;

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## This note was uploaded on 06/20/2011 for the course EE 2730 taught by Professor Desouza during the Spring '08 term at LSU.

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HW4soln-2730-F08 - EE 2730 HW 4 solutions EE 2730 Homework...

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