1
EE 2730 — Test 1 solutions
Fall 2008
1.
(20 pts)
Consider the timing diagram below, where
D
and
Clock
are inputs to three
storage elements:
a D latch with output
Q
L
, a positive edge triggered D flip-flop with output
Q
PE
,
and a negative edge triggered D flip-flop with output
Q
NE
.
Draw waveforms for the
Q
L
,
Q
PE
, and
Q
NE
signals, assuming that each output is initially 0.
(Assume ideal elements with no
propagation delay.)
2.
(15 pts)
Can the feedback circuit in the figure below function as a basic SR latch?
Explain.
If so, then which input would be S and which R?
No, the circuit cannot function as an SR latch.
If C = 1, D = 0 and inputs A = B = 0 are
applied, then outputs oscillate to C = 0, D = 1 then C = 1, D = 0, etc., while for an SR latch with
S = R = 0, the outputs would not change.
If C = 1, D = 0 and inputs A = 0, B = 1 are applied,
then C and D keep changing in sequence (C changes to 0, then D changes to 1, then C changes to
1, then D changes to 0, then C changes back to 0, etc.).
The circuits behaves similarly for A = 1,