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Unformatted text preview: 2 (b) Using D flip-flops: Y 1 = w y 1 + wy Y = w y + wy 1 z 1 = y 1 z = y 3. (30 pts) Write Verilog code to specify the finite-state machine shown below, with one input w and one output z . module T2P4 (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y, Y; parameter [2:1] A = 2b00, B = 2b01, C = 2b10, D = 2b11; // Define the next state combinational circuits always @(w, y) case (y) A: if (w) Y = C; else Y = B; B: Y = C; C: if (w) Y = D; else Y = A; D: if (w) Y = C; else Y = D; default : Y = 2bxx; // optional endcase // Define the sequential block always @( negedge Resetn, posedge Clock) if (Resetn == 0) y <= A; else y <= Y; // Define the output circuit assign z = ((y = = C) | (y = = D)); endmodule EE 2730 Test 2 solutions 3 4. (20 pts) Represent the finite-state machine from Problem 3 in the form of an ASM chart....
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This note was uploaded on 06/20/2011 for the course EE 2730 taught by Professor Desouza during the Spring '08 term at LSU.
- Spring '08