HW4soln-2730-S11

# HW4soln-2730-S11 - EE 2730 HW 4 solutions EE 2730 Homework...

This preview shows pages 1–3. Sign up to view the full content.

EE 2730 — HW 4 solutions 1 EE 2730 — Homework 4 solutions Spring 2011 1. The state diagram below, from Homework 3 #1, is for a 1’s counting circuit with two inputs, a and b , and one output, z . The label on each edge denotes the values of ab ; the number in each state circle is z . Write Verilog code for this circuit. module prob4_1 (Clock, Resetn, a, b, z); input Clock, Resetn, a, b; output reg z; reg [2:1] y, Y; parameter [2:1] A = 2’b00, B = 2’b01, C = 2’b11, D = 2’b10; // Define the next state combinational circuit always @(a, b, y) case (y) A: case ({a,b}) 2’b00: Y = A; 2’b01: Y = B; 2’b10: Y = B; 2’b11: Y = C; endcase B: case ({a,b}) 2’b00: Y = B; 2’b01: Y = C; 2’b10: Y = C; 2’b11: Y = D; endcase C: case ({a,b}) 2’b00: Y = C; 2’b01: Y = D; 2’b10: Y = D;

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
EE 2730 — HW 4 solutions 2 2’b11: Y = A; endcase D: case ({a,b}) 2’b00: Y = D; 2’b01: Y = A; 2’b10: Y = A; 2’b11: Y = B; endcase endcase // Define the sequential block always @( negedge
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 06/20/2011 for the course EE 2730 taught by Professor Desouza during the Spring '08 term at LSU.

### Page1 / 4

HW4soln-2730-S11 - EE 2730 HW 4 solutions EE 2730 Homework...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online