Test1soln-2730-S11

Test1soln-2730-S11 - is to receive the value of A ! B , and...

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EE 2730 — Test 1 solutions 1 EE 2730 — Test 1 solutions Spring 2011 1. (20 pts) Sketch the Q and outputs of a positive-edge-triggered JK flip-flop for the input waveforms shown below. Assume only a small propagation delay for the latch as a whole (that is, you need not be concerned about timing differences between the Q and outputs). 2. (15 pts) For the feedback circuit below, determine the new values for y and z for the initial values of w , x , y , and z shown in the table below. w x y (old) z (old) y (new) z (new) 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 0 1 0 3. (25 pts) Use D flip-flops, along with gates and multiplexers as needed, to design a binary counter with the following repeated binary sequence: 0, 1, 2.
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EE 2730 — Test 1 solutions 2 4. (25 pts) Write Verilog code for the following sequential circuit. Asynchronously clear an 8-bit register A to all 0’s when resetn = 0. Synchronously, for an 8-bit input B and a 1- bit input c , when c = 0, A
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Unformatted text preview: is to receive the value of A ! B , and when c = 1, A is to receive the value of + (where denotes AND and + denotes OR). module prob4(A, B, c, resetn, clock); parameter n = 8; input [n-1:0] B; input c, clock, resetn; output reg [n-1:0] A; always@(negedge resetn, posedge clock) if (!resetn) A <= 0; else if (c == 0) A <= A&B; else A <= A | (~B); endmodule 5. (15 pts) For the circuit below, calculate the minimum period of the clock signal, T min , , and determine whether any hold time violations occur in the circuit. Assume for a T flip-flop that t su = 0.6 ns, t h = 0.4 ns, 0.8 ns t cQ 1.0 ns. Assume that the delay through any logic gate can be calculated as 1 + 0.1 k ns, where k is the number of inputs to the gate. The circuit below is Figure 7.22(a) in Brown and Vranesic. T min = t cQ + 2( t AND ) + t su = 1.0 + 2(1.2) +0.6 ns = 4.0 ns t cQ is shortest path = 0.8ns > 0.4 ns, so no hold time violation...
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Test1soln-2730-S11 - is to receive the value of A ! B , and...

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