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Unformatted text preview: is to receive the value of A ! B , and when c = 1, A is to receive the value of + (where ⋅ denotes AND and + denotes OR). module prob4(A, B, c, resetn, clock); parameter n = 8; input [n1:0] B; input c, clock, resetn; output reg [n1:0] A; [email protected](negedge resetn, posedge clock) if (!resetn) A <= 0; else if (c == 0) A <= A&B; else A <= A  (~B); endmodule 5. (15 pts) For the circuit below, calculate the minimum period of the clock signal, T min , , and determine whether any hold time violations occur in the circuit. Assume for a T flipflop that t su = 0.6 ns, t h = 0.4 ns, 0.8 ns ≤ t cQ ≤ 1.0 ns. Assume that the delay through any logic gate can be calculated as 1 + 0.1 k ns, where k is the number of inputs to the gate. The circuit below is Figure 7.22(a) in Brown and Vranesic. T min = t cQ + 2( t AND ) + t su = 1.0 + 2(1.2) +0.6 ns = 4.0 ns t cQ is shortest path = 0.8ns > 0.4 ns, so no hold time violation...
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 Spring '08
 DeSouza
 Logic gate, Flipflop, Small propagation delay, positiveedgetriggered JK flipflop

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