04 verilog-combl

04 verilog-combl - Verilog - review for combinational...

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Verilog - review for combinational circuits EE 2730 2 Relevant sections of Brown and Vranesic §2.10 - Introduction to Verilog §4.12 - Examples of Circuits Synthesized from Verilog Code §5.5 - Design of Arithmetic Circuits Using CAD Tools §6.6 - Verilog for Combinational Circuits Appendix A - Verilog Reference
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source: Brown and Vranesic (2008) 3 Structural specification f x 3 x 1 x 2 Figure 2.30. A simple logic function. module example1 (x1, x2, x3, f); input x1, x2, x3; output f; and (g, x1, x2); not (k, x2); and (h, k, x3); or (f, g, h); endmodule Figure 2.31. Verilog code for the circuit in Figure 2.30. source: Brown and Vranesic (2008) 4 Behavioral specification f x 3 x 1 x 2 Figure 2.30. A simple logic function. module example3 (x1, x2, x3, f); input x1, x2, x3; output f ; assign f = (x1 & x2) | (~x2 & x3); endmodule Figure 2.34. Using the continuous assignment to specify the circuit in Figure 2.30.
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source: Brown and Vranesic (2008) 5 Behavioral specification 2 module example3 (x1, x2, x3, f); input x1, x2, x3; output f ; assign f = (x1 & x2) | (~x2 & x3); endmodule Figure 2.34. Using the continuous assignment to specify the circuit in Figure 2.30. // Behavioral specification module example5 (x1, x2, x3, f); input x1, x2, x3; output f ; reg f ; always @(x1 or x2 or x3) if (x2 == 1) f = x1; else f = x3; endmodule Figure 2.36. Behavioral specification
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04 verilog-combl - Verilog - review for combinational...

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