05 verilog-storage

05 verilog-storage - Verilog for storage elements EE 2730...

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Verilog for storage elements EE 2730 2 Implied memory if-else statement can specify storage element describe desired behavior in response to changes in levels of data and clock inputs always @ (control or B) if (control) A = B; // A is variable of reg type Does not say what happens when control = 0 In absence of an assigned value, Verilog compiler assumes value of A caused by if statement must be maintained until next time if statement evaluated. Implied memory realized by a latch in the circuit.
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source: Brown and Vranesic (2008) 3 D latch and flip-flop module D_latch (D, Clk, Q); input D, Clk; output reg Q; always @(D, Clk) if (Clk) Q = D; endmodule Figure 7.35. Code for a gated D latch. module flipflop (D, Clock, Q); input D, Clock; output reg Q; always @( posedge Clock) Q = D; endmodule Figure 7.36. Code for a D flip-flop. 4 Blocking and non-blocking assignment Blocking assignment Example: Q = D; Verilog compiler in always block evaluates statements in the order in
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This note was uploaded on 06/20/2011 for the course EE 2730 taught by Professor Desouza during the Spring '08 term at LSU.

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05 verilog-storage - Verilog for storage elements EE 2730...

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