07 T1_review_S11

07 T1_review_S11 - Review for Test 1 EE 2730 Survey results...

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Review for Test 1 EE 2730 2 Survey results - least understood registers and/or counters 13 Verilog 11 flip-flops 6 design specified circuit 5 timing analysis 4 drawing circuits 2 other 5
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3 Shift register Homework 2 #2 - A universal shift register can shift in both the left- to-right and right-to-left directions, and it has parallel-load capability. Draw a circuit for such a shift register. 4 Counter F08 Homework 2 #4 - Construct a 16-bit synchronous counter, using four 4-bit synchronous counters (as in Figure 7.24). Suppose serial connections are employed between the four counters. What is the maximum number of AND gates in a chain that a signal must propagate through in the 16-bit counter?
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5 Counter F08 Homework 2 #4 - Construct a 16-bit synchronous counter, using four 4-bit synchronous counters (as in Figure 7.24). Suppose serial connections are employed between the four counters. What is the maximum number of AND gates in a chain that a signal must propagate through in the 16-bit counter? 6
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This note was uploaded on 06/20/2011 for the course EE 2730 taught by Professor Desouza during the Spring '08 term at LSU.

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07 T1_review_S11 - Review for Test 1 EE 2730 Survey results...

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