09 ch8-VerilogFSM8.4

# 09 ch8-VerilogFSM8.4 - else y<= A C if(w y<= C else...

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Verilog for Finite-State Machines EE 2730 2 module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y, Y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the next state combinational circuit always @(w, y) case (y) A: if (w) Y = B; else Y = A; B: if (w) Y = C; else Y = A; C: if (w) Y = C; else Y = A; default : Y = 2'bxx; endcase // Define the sequential block always @( negedge Resetn, posedge Clock) if (Resetn = = 0) y <= A; else y <= Y; // Define output assign z = (y = = C); endmodule Figure 8.29. Verilog code for the FSM in Figure 8.3. C z 1 = / Reset B z 0 = / A z 0 = / w 0 = w 1 = w 1 = w 0 = w 0 = w 1 =

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3 module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the sequential block always @( negedge Resetn, posedge Clock) if (Resetn = = 0) y <= A; else case (y) A: if (w) y <= B; else y <= A; B: if (w) y <= C;
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Unformatted text preview: else y <= A; C: if (w) y <= C; else y <= A; default : y <= 2'bxx; endcase // Define output assign z = (y = = C); endmodule Figure 8.34. Third version of code for the FSM in Figure 8.3. C z 1 = / Reset B z 0 = / A z 0 = / w 0 = w 1 = w 1 = w 0 = w 0 = w 1 = 4 module mealy (Clock, Resetn, w, z); input Clock, Resetn, w; output reg z; reg y, Y; parameter A = 1’b0, B = 1’b1; // Define the next state and output combinational circuits always @(w, y) case (y) A: if (w) begin z = 0; Y = B; end else begin z = 0; Y = A; end B: if (w) begin z = 1; Y = B; end else begin z = 0; Y = A; end endcase // Define the sequential block always @( negedge Resetn, posedge Clock) if (Resetn = = 0) y <= A; else y <= Y; endmodule Figure 8.36. Verilog code for the Mealy machine of Figure 8.23....
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09 ch8-VerilogFSM8.4 - else y<= A C if(w y<= C else...

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