10 ch8-seqDesign8.5

10 ch8-seqDesign8.5 - // Output and next state...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Sequential circuit design Sec. 8.5 — Serial adder EE 2730 2 module shiftrne (R, L, E, w, Clock, Q); parameter n = 8; input [n-1:0] R; input L, E, w, Clock; output reg [n-1:0] Q; integer k; always @( posedge Clock) if (L) Q <= R; else if (E) begin for (k = n-1; k > 0; k = k-1) Q[k-1] <= Q[k]; Q[n-1] <= w; end endmodule Figure 8.48. Code for a left-to-right shift register with an enable input.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
3 module serial_adder (A, B, Reset, Clock, Sum); input [7:0] A, B; input Reset, Clock; output wire [7:0] Sum; reg [3:0] Count; reg s, y, Y; wire [7:0] QA, QB; wire Run; parameter G = 1 ` b0, H = 1 ` b1; shiftrne shift_A (A, Reset, 1 ` b1, 1 ` b0, Clock, QA); shiftrne shift_B (B, Reset, 1 ` b1, 1 ` b0, Clock, QB); shiftrne shift_Sum (8 ` b0, Reset, Run, s, Clock, Sum); // Adder FSM
Background image of page 2
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: // Output and next state combinational circuit always @(QA, QB, y) case (y) G: begin s = QA[0] ^ QB[0]; if (QA[0] & QB[0]) Y = H; else Y = G; end H: begin s = QA[0] ~^ QB[0]; if (~QA[0] & ~QB[0]) Y = G; else Y = H; end default : Y = G; endcase // Sequential block always @( posedge Clock) if (Reset) y <= G; else y <= Y; // Control the shifting process always @( posedge Clock) if (Reset) Count = 8; else if (Run) Count = Count - 1; assign Run = |Count; endmodule Figure 8.49. Verilog code for the serial adder. 4 Adder FSM Clock E w L E w L b 7 b 0 a 7 a 0 E w L E L Q 3 Q 2 Q 1 Q 0 D 3 D 2 D 1 D 0 1 0 0 0 Counter 0 0 Reset Sum 7 Sum 0 0 1 0 1 Run Figure 8.50. Synthesized serial adder....
View Full Document

This note was uploaded on 06/20/2011 for the course EE 2730 taught by Professor Desouza during the Spring '08 term at LSU.

Page1 / 2

10 ch8-seqDesign8.5 - // Output and next state...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online