12 T2_review_S11

12 T2_review_S11 - Review for Test 2 EE 2730 Survey results...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Review for Test 2 EE 2730 2 Survey results - least understood Verilog 21 Mealy 5 state minimization/ incompletely specified FSM 5 arbiter 5 design with JK, T flip-flops 4 counters 3 other 9 includes serial adder, ASM, design (generally), flip-flops
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
3 Verilog examples module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y, Y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the next state combinational circuit always @(w, y) case (y) A: if (w) Y = B; else Y = A; B: if (w) Y = C; else Y = A; C: if (w) Y = C; else Y = A; default : Y = 2'bxx; endcase // Define the sequential block always @( negedge Resetn, posedge Clock) if (Resetn = = 0) y <= A; else y <= Y; // Define output assign z = (y = = C); endmodule module mealy (Clock, Resetn, w, z); input Clock, Resetn, w; output reg z; reg y, Y; parameter A = 1 ` b0, B = 1 ` b1; // Define the next state and output combinational circuits always @(w, y) case (y) A: if (w) begin z = 0;
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 06/20/2011 for the course EE 2730 taught by Professor Desouza during the Spring '08 term at LSU.

Page1 / 5

12 T2_review_S11 - Review for Test 2 EE 2730 Survey results...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online