13 ch10-digitalSysDesign

13 ch10-digitalSysDesign - Chapter 10 — Digital System...

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Unformatted text preview: Chapter 10 — Digital System Design EE 2730 flip-flop with enable • Figure 10.1. A flip-flop with an enable input • good • Figure 10.43. Clock enable circuit • flawed 2 D Q Q Q R Clock E 0 1 D Q Q Data Clock E flip-flop with enable - Verilog • Figure 10.1. A flip-flop with an enable input 3 D Q Q Q R Clock E 0 1 module rege (R, Clock, Resetn, E, Q); input R, Clock, Resetn, E; output reg Q; always @( posedge Clock, negedge Resetn) if (Resetn == 0) Q <= 0; else if (E) Q <= R; endmodule Figure 10.2. Code for a D flip-flop with enable shift register with enable 4 Figure 10.4. A shift register with parallel-load and enable control inputs. bit counter Figure 10.9. Pseudo- code for the bit counter 5 B = 0 ; while A ! 0 do if a = 1 then B = B + 1 ; end if; Right-shift A ; end while; Shift right A Done B B 1 + ! A 0 = ? B 0 ! s Load A a 0 Reset S3 0 1 0 1 0 1 s S1 S2 1 0 Figure 10.10. ASM chart for the pseudo-code in Figure 10.9. bit counter - datapath 6 Figure 10.11. Datapath for the ASM chart in Figure 10.10. bit counter – ASM for control 7 EA EB z LB s a 0 Reset S3 0 1 0 1 0 1 s S2 S1 0 1 Done Figure 10.12. ASM chart for the bit counter datapath circuit....
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This note was uploaded on 06/20/2011 for the course EE 2730 taught by Professor Desouza during the Spring '08 term at LSU.

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13 ch10-digitalSysDesign - Chapter 10 — Digital System...

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