ece290exam2f09soln - ECE 290 MIDTERM EXAM#2 Tuesday...

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ECE 290 MIDTERM EXAM #2 Fall 2009 Tuesday, November 17, 2009 7-8:30pm Closed Book You are allowed one 8.5 x 5.5 inch sheet of notes No cell phones, calculators, headphones, etc. This exam contains 14 pages including this cover sheet. Be sure you have all the pages. The questions are not weighted equally, so budget your time accordingly. If you feel that a question is ambiguous, then give your reasons and state your assumptions. Write your answers on these pages. Show all your work. If your work is not shown, then you risk receiving no credit. Excess complexity will be penalized. Use backs of pages for scratch work if needed. PRINT NAME: SIGNATURE: Indicate your section: ( ) AD2 Th 9 Tenzing Shaw 1. (11%) _________________________ ( ) AD3 Th 10 Tenzing Shaw 2. (6%) _________________________ ( ) AD4 Th 11 Joseph Sloan 3. (10%) _________________________ ( ) AD5 Th 12 Joseph Sloan 4. (15%) _________________________ ( ) AD6 Th 1 Scott Chen 5. (7%) _________________________ ( ) AD7 Th 2 Joshua Juen 6. (17%) _________________________ ( ) AD8 Th 3 Michael Rogers 7. (11%) _________________________ 8. (14%) _________________________ 9. (9%) _________________________ Total. (100%) _________________________
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Page 2 of 25 Name: Problem 1. (11%) The sequential circuit shown below has a positive-edge-triggered JK flip-flop, a positive-edge-triggered D flip-flop, a 1-to-2 demultiplexer, an XOR gate and an unknown combinational circuit labeled as U with two inputs and one output. The sequential circuit has two inputs X and Y, and three outputs Z, d 0 and d 1 . Complete the timing diagram below for Q B, Q A , J A , Z, d 0 and d 1 . Ignore delays. Place a question mark over a region where a value cannot be determined.
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Page 3 of 25 Name:
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Page 4 of 25 Name: Solution:
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Page 5 of 25 Name: Problem 2. (6%) A sequential circuit is given below with the following timing parameters: Inverter: propagation delay = 0.75ns XOR gate: propagation delay =1.5ns Flip-flop: propagation delay =2.0ns, setup time =1.0ns Find the followings three values. Show your work (e.g., write 2ns + 1ns) (a) The longest path delay from the input X to the output Y: (b) The longest path delay from positive clock edge to positive clock edge: (c) The longest path delay from positive clock edge to the output Y.
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Page 6 of 25 Name: Solution (a) The longest path delay from the input X to the output Y: (XOR + XOR) = 1.5+1.5=3ns (b) The longest path delay from positive clock edge to positive clock edge:
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This note was uploaded on 06/21/2011 for the course ECE 290 taught by Professor Staff during the Spring '08 term at University of Illinois, Urbana Champaign.

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ece290exam2f09soln - ECE 290 MIDTERM EXAM#2 Tuesday...

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