ece290exam2sp10soln.pdf

ece290exam2sp10soln.pdf - ECE 290 Z. K albarczyk, S. V...

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ECE 290-Spring 2010 Page 2 Name: Problem 1 (10%) a) Design a synchronous counter for a digital watch that counts in minutes and seconds. You are given a 6-bit synchronous binary counter chip with synchronous Load and synchronous Count-Enable signals shown in the figure below. When both Load and Count-Enable are enabled, the counter only loads the data at the positive edge of the clock signal. In the watch application, the count goes from 1 to 60 and repeats (which is slightly different from a true modulo-60 counter that counts from 0 to 59 and repeats). Show the necessary connections and inputs in the figure, using as few gates as possible. Output Y should be 1 when the counter reaches 60. You need to specify values to all inputs of the counter. (Note: 60i 0 = 111100 2 ). b) CLK count "~L I _J \ Q o 1 CTR-6 > clock Inorl O5 count-enable Q4 D5 /",o Q3 D4 /-in Q2 D3 r\* UO Q1 D2 r\r\ * QO m DO ~"7=r~y-n T — J ^ } Y Interconnect the Second-Counter and the Minute-Counter shown below with the minimal logic such that for every 60 cycles in the Second-Counter, the Minute-Counter is incremented by 1. (You may assume that each of the following counters is built using the counter as specified in part (a).) You need to specify the values to all the inputs of the counters.
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This note was uploaded on 06/21/2011 for the course ECE 290 taught by Professor Staff during the Spring '08 term at University of Illinois, Urbana Champaign.

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ece290exam2sp10soln.pdf - ECE 290 Z. K albarczyk, S. V...

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