2011) - Mallard Intro to Computer Engineering I Written...

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Written Hwk #8 (due 3/16/2011) ECE 290 Problem Set #8 Due: October 20, 2010 Problem 8.0 (Midterm I Question 5) In thinking about the propagation delay of a ripple-carry adder, we see that the higher-order bits are "waiting" for their carry-ins to propagate up from the lower-order bits. This is a Ripple Carry Adder(RCA). Suppose we split off the high-order bits and create two separate adders: one assuming that the carry-in was 0 and the other assuming the carry-in was 1. Then when the correct carry-in is available from the low-order bits, it could be used to select which high-order sum to use. This is called a Carry Select Adder (CSA). The diagram below shows this strategy applied to an 8-bit adder. Compare the latency in computing S[7] in the 8-bit CSA shown above to a regular 8-bit RCA. Assume the 4-bit adders are also RCAs. Assume that the delay of any gate is 1 unit and the delay of a multiplexer is 3 units. The circuit for the full-adders is the same as one which you did in your labs (except for the delays) a. Compare the delay in the computation of S[7] between the following : A 8-bit Carry Lookahead Adder (with no carry selection) and A Carry Select Adder in which two 4-bit Carry Lookahead Adders are used (instead of the two 4-bit RCAs) b. If this was a 16-bit carry select adder with two 8-bit ripple carry adders, how would the delay of the multiplexer change? i. Can you now guess which one would be faster, carry select or ripple carry, as the number of operand bits N increases? ii. c.
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This note was uploaded on 06/21/2011 for the course ECE 290 taught by Professor Staff during the Spring '08 term at University of Illinois, Urbana Champaign.

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2011) - Mallard Intro to Computer Engineering I Written...

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