Written Hwk #8 (due 3/16/2011)
ECE 290
Problem Set #8
Due: October 20, 2010
Problem 8.0 (Midterm I Question 5)
In thinking about the propagation delay of a ripplecarry adder, we see that the higherorder bits are "waiting" for their carryins to propagate up from the lowerorder bits. This is a Ripple Carry Adder(RCA). Suppose we split off
the highorder bits and create two separate adders: one assuming that the carryin was 0 and the other assuming the carryin was 1. Then when the correct carryin is available from the loworder bits, it could be used to select
which highorder sum to use. This is called a Carry Select Adder (CSA). The diagram below shows this strategy applied to an 8bit adder.
Compare the latency in computing S[7] in the 8bit CSA shown above to a regular 8bit RCA. Assume the 4bit adders are also RCAs.
Assume that the delay of any gate is
1 unit
and the delay of a multiplexer is
3 units.
The circuit for the fulladders is the same as one which you did in your labs (except for the delays)
a.
Compare the delay in the computation of S[7] between the following :
A 8bit Carry Lookahead Adder (with no carry selection) and
A Carry Select Adder in which two 4bit Carry Lookahead Adders are used (instead of the two 4bit RCAs)
b.
If this was a 16bit carry select adder with two 8bit ripple carry adders, how would the delay of the multiplexer change?
i.
Can you now guess which one would be faster, carry select or ripple carry, as the number of operand bits N increases?
ii.
c.
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 Spring '08
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 Carry lookahead adder, RCA

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