Written Hwk #9 (due 3/30/2011)
ECE 290
Problem Set #9
Due: March 30, 2011
Problem 9.1
Consider a 3-bit twisted ring counter consisting of 3 D Fip-Fops (labelled C, B, A from left-to-right) and an inverter, connected such that DB = QC, DA = QB, and DC = QA'.
Starting with state QCQBQA = 111, give the counting sequence in binary.
a.
Which states are illegal? Verify that the circuit is not self-correcting by showing the count sequence(s) for these illegal states.
b.
Modify the DC input to be DC = QCQB' + QA'. Verify that this modi±ed circuit is self-correcting.
c.
Problem 9.2
Implement a mod 6 counter which counts in the following CBA sequence and repeats: 111, 010, 100, 001, 101, 000. I.e., the counter proceeds through its 6 states in the (nonstandard) order 7, 2, 4, 1, 5, 0.
Draw the state diagram for this counter.
Note:
There are no "input/output" labels on the edges, because there is no input (other than the clock) and the output is just the state.
a.
You will implement the counter using 3 T Fip-Fops. Draw the next state/excitation table, showing the current state CBA, the next state C
+
B
+
A
+
, and the Fip-Fop excitation inputs T
C
T
B
T
A
.
b.
Give the K-maps and provide minimal SOP expressions for T
C
, T
B
, T
A
.
c.
Draw the augmented state diagram; i.e., include the don't care states. Is this counter self-starting? Explain.
d.
Modify your circuit so that, from any don't care state, the next state will be 000. Show your work.
Hint:
Go back to part (c) to make the necessary changes.
e.
Problem 9.3
Design a 4-bit register, whose inputs and outputs are as shown in the diagram below. The mode operation table is also given under the diagram.
M
0
M
1
M
2
Operation
0
0
0
No Change
0
0
1
Logical Shift Right
0
1
0
Logical Shift Left
0
1
1
Increment value by 1
1
0
0
Clear all bits
1
0
1
Complement all bits
1
1
0
Arithmetic Shift Right
1
1
1
Parallel Load
Use D Fip-Fops to implement the PISO (Parallel-in Serial-Out) shift register. You can use this as a block N in your ±nal design.