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ece290Written Hwk #11 (due April 13, 2011)

ece290Written Hwk #11 (due April 13, 2011) - Mallard Intro...

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Written Hwk #11 (due April 13, 2011) ECE 290 Problem Set #11 Due: April 13, 2011 ©D. J. Brown Problem 11.1. Booth's Algorithm for Multiplication and hardwired control unit design. You must use the worksheet provided. Before doing this problem, you should read the Booth's Algorithm tutorial on Mallard. Also read carefully the notes for the multiplier implementation done in lecture. In the block diagram for the binary multiplier done in lecture, write c n for the carry-out from the last (leftmost) stage and c n -1 for the carry into that stage of the adder, and let s n -1 be the leftmost bit of the result computed by the adder. Assuming that the values in registers A and B are represented in two's complement form, explain why the sign bit of the actual sum should be c n xor c n -1 xor s n -1 , even if overflow occurs. a. Draw an ASM chart for Booth's algorithm. This should be very similar to the unsigned binary multiplication ASM done in lecture, consisting of states IDLE, MUL0, and MUL1.
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