exam2_f05 - ECE 290 University of Illinois Fall 2005 HOUR...

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Unformatted text preview: ECE 290 University of Illinois Fall 2005 HOUR EXAM II / November 16, 2004/9 You are allowed one 8.5 x 11 inch sheet of notes. N0 electronic devices of any kind are allowed. This exam contains 7 questions. Write your answers on these pages. Show all your work. If your work is not shown, you risk receiving no credit. Use backs of pages for scratch work if needed. Be sure you have completed all parts of each question. Turn in all 10 pages of the exam. Put your name on every page. Point counts for each each problem are given. Budget your time accordingly. If you feel that a question is ambiguous, give your reasons and state your assumptions. PRINT NAME S I GN ATURE SECTION NUMBER / SECTION TA : ----------------------------------------------- -- quenwn s «mm-en (cottages? ARK-M‘I'ECWRE TOTAL Problem 1. (20 points) Reminder: For all your designs, excess complexity will be penalized. Shown below is a mod 16 synchronous counter, which counts in order: QDQCQBQA = 0000, 0001, 0010, 0011, 0100, 1110, 1111, 0000, clock (a) Suppose it is desired to add a synchronous clear signal to the above Circuit. Show how the input to each T flip-flop would be modified so as to respond to the CLR input: CLR = 1 resets QDQCQBQA to 0000 at the next clock pulse. Draw the modification for the one T flip-flop shown below. You may use AND, OR, NOT gates, multiplexers, decoders as needed. 0) O clock (b) Modify the mod 16 synchronous counter given above so that it counts in the sequence 0, 1, 2, 3, 4, 8, 9, 10, 11, 12, 13, 14, 15, 0, Note that it counts in normal order except when it skips from 4 to 8. (i) Briefly explain what modifications are needed. Give your strategy, not boolean expression details. Note: you are modifying the mod 16 counter, not designing from scratch. (ii) Complete the circuit drawn below, using at most 7 AND, OR, NOT gates. clock Problem 1 (cont) (c) Design a circuit such that when the input x goes to 1 during one clock period, then the output 2 will be the next 5 consecutive clock pulses. 2 will be 0 at all other times. (Assume that x remains 0 throughout the time that 2 can have nonzero output.) x ___l_|______—_____ Given below is the counter from part (b) together with clear and enable inputs. Draw the additional Circuitry so that the circuit behaves as specified; do not modify the counter and keep the enable input at 1. counter (from part b) C K o QUESTION 2 (10 pts.) Name You have three functional units with the following descriptions. U L has 2 16—bit inputs 0. and b, 2 control inputs 51 and 30; unit U A has 2 16—bit inputs 0 and d, 1 control input 32, and produces a 16—bit result; unit U1 has 1 16-bit input e, 1 control input 33 and produces a 16-bit result. The function tables for each unit appear below. 5'1 50 0 1 not(b) 1 0 a and b 1 1 a or b Inter-connect these units so as to create a functional unit F that accepts two 16-bit inputs A and B, ‘ accepts two function bits f1 and f0, and produces 1 16-bit output according to the table o For each of F’s functions, describe in English how the three units contribute to its creation 0 Keep the amount of extra logic as small as you can. In particular, don’t use any muxes or decoders. Label all the components used. 0 Give input equations for the control input signals of each unit, / \\\ / QUESTION 3 (10 pts.) Name ._____.___—_._ Consider the state transition diagram below. Each transition are is labeled with control inputs c1co that induce that transition on the next clock. Design the circuit that implements this state machine. Use 2 JK flip—flops to hold the state. Name the outputs of those flip-flops X1, and X0 so that the state number is XlXo. Use J1- and K,- to name the J and K inputs of X;. Give the minimal SOP input equations for each in the table below (Use the back side for your derivations, if needed.) // QUESTION 4 (10 pts.) Name We are to build a 23° _>< 8 memory, using 227 x 8 chips. Each chip has 27 address lines, a chip enable line EN, a read/ write line RW (has value 1 on a read, value 0 on a write), 8 data lines in that carry the 8 bits on a write, and 8 data lines out that carry the 8 bits on a read. [2 pts.] How many memory chips do we need to use? [8 pts.] Design this memory using coincident addressing. The overall memory is to have 30 address lines, 8 data input lines, 8 data output lines, a R/ W line, and an enable line EN. Draw a diagram, being sure to label all muxes, decoders, registers, buses, tri—state buffers, etc. that make up the design. QUESTION 6 (20 pts.) Name The instruction fetch sequence for every LC—3 instruction goes through four states : 18, 33, 35, and 32, ' as seen on the attached LC-3 state transition diagram. The table below lists relevant control signals on the LC—3 data path. In each column (one per state) place a check mark in the row corresponding to a control signal that must be specified in that state for correct operation. Leave blanks for control signals for which don’t cares apply. We are not asking that you specify what the value is. We are asking you to identify the control signals which are not don’t cares. Also specify branching code (COND(2:_0)), and the jump index (J) required for each state. You may state the jump index in decimal. Control Signal State 18 State 33 State 35 State 32 GateMARMUX —_—_ MARMUX __— GatePc __— LDPC —_—— Pc-MUx __— DR ———_ LDREG --_— SR1 __— SR2 —__— ADDRIMUX ——_— ADDR2MUX __— LDIR __-— LD.CC __— GateALU __— GateMDR _—_— LD-MDR __- LDMAR _——— MIOEN __— R-w __— IRD —_—_ Branching Code (COND2 CONDl CONDO) 3-bit branch code Jump Vector Value in Microdnstruction (J [5] J [4] J [3] J [2] J [1] J QUESTION 7 (10 pts.) Name 0 Identify two ways in which the LC—3 ISA supports subroutine calls. For each, explain why either the function must be provided by hardware, or could be provided at higher execution cost in software. a In some architectures the program counter is a general register, accessible as the source and/ or desti- nation for any normal register—to-register operation. What hardware support—if any—is necessary to support subroutine calls on such a machine? re 0.7) )2. .2. appendix c The Microarchitecture of the LC-3 15 MAR <—PC PC<—PC+1 [INT] 1 o 33 To 49 . MDH<_M (See Figure 6.7) F] Fl 35 lR<—M DR 32 mi ' 1101 BEN<—IR[11]& N + lFi[10] & Z + IR[9] & P ADD [IR[15:12]] BR AND nor JMP m9 JSR LD LDR LDl ST! STR ST CONDZ COND1 interrupt present User privilege mode JIZ] Address of next state Figure C5 The microsequencer of the LC-3 CONDO Fi coke 3.3 To 13 [Bi 0 o O X o ‘ ‘ X 1 O X I ( l X 0 ...
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exam2_f05 - ECE 290 University of Illinois Fall 2005 HOUR...

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