Delay in FA Circuits - Mallard ECE 290: Computer...

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Mallard ECE 290: Computer Engineering I - Spring 2007 - Graded Web. .. https://mallard.cites.uiuc.edu/ECE290/webgrade.cgi?SessionID=mding3. .. 1 of 3 2/5/2007 3:07 PM Graded WebQuiz: Delay in FA Circuits You have submitted this WebQuiz 3 times (including this time). You may submit this WebQuiz a total of 10 times and receive full credit. Question #1 Consider the FA circuit implementation shown below, along with the specified gate delays. Gate delays: AND 2 ns OR 1 ns XOR 2 ns Part (a) Fill in the appropriate gate output values in the table below. Assume that the FA circuit is stable prior to time 20 with A=0, B=1, C in =1. Then at time 20 the inputs change to A=1, B=1, C in =0. time (ns) A B Cin G1 G2 G3 G4=S G5=Cout before time 20 0 1 1 1 0 1 0 1 20 1 1 0 1 0 1 0 1 21 1 1 0 1 0 1 0 1 22 1 1 0 0 1 0 1 1 23 1 1 0 0 1 0 1 1 24 1 1 0 0 1 0 0 1 25 1 1 0 0 1 0 0 1 26 1 1 0 0 1 0 0 1 Part (b) Suppose 37 of these full adders are connected so as to form a 37-bit ripple adder. What is the maximum possible delay of this ripple adder? (I.e., what is the maximum possible delay before
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This note was uploaded on 06/21/2011 for the course ECE 290 taught by Professor Staff during the Spring '08 term at University of Illinois, Urbana Champaign.

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Delay in FA Circuits - Mallard ECE 290: Computer...

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