hwk05_s07_soln - 3;; an a i 3:3: i?" riot stapled...

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Unformatted text preview: 3;; an a i 3:3: i?" riot stapled Name: I V' Section: .;§§l§iilliiiv;giw Score: Homework Set 5 ©D. J. Brown & C. N. Hadjicostis Due Wednesday, February 21, 2007 at 3pm Exam #1 Tuesday, February 27 7:00-8: 15pm If you have a legitimate conflict with the exam time you must send email to Prof. Hadjicostis ([email protected]) by Monday, February 3.9 at the latest, providing the following information: 1) Your name, netID, and section 2) Precise details of the conflict e.g., physics 112 lab, section X3, 7—9 pm; 3) Your availability that evening (both before and after exam time), e.g., 5:30-10:00 pm Label MSI Components Carefully This assignment focuses on logic design using MSI (Medium—Scale Integration) components such as multiplexers, demultiplexers, encoders, and decoders. For each MSI component used in your designs, you must be careful to iale aii inputs and outputs (e.g. 3:8 decoder select lines 525150 and output lines I7I5...lo) as well as the MSI components tl'iemselves (e.g. for a 3:8 decoder, the words “3:8 DEC" must appear on the “box”). Points will be deducted on each problem if your MSI components are not fully and correctly labeled. Problem 5.0 Do Week #5 Mallard quizzes due 3 pm Tuesday. Problem 5.1 In each part of this problem, you will draw a combinational circuit which implements all three of the following functions (f, g, and h). Complemented inputs are not available. f(x,y,z) = (y XOR z) + x2' 9(x,v.z) = xv + v'z' h(x,y,z) = y XOR 2 (continued on next page) Problem 5.1 (continued) Clear/y label each component’s inputs and outputs and the components themselves. a. Implement f, g, and h using only one 3-to-8 decoder, two 4-input OR gates, and one 4-input NOR gate. Draw the circuit. 2395?“? 3'? f V , b. Implement f, g, and h using only three 4-to-1 MUX's and, if necessary, one inverter. int-3t 357. be the 33-1, 5.3 select énputs for each MUX. Draw the circuit. Problem 5.1 (continued) Clearly label each component’s inputs and outputs and the components themselves. c. Implement f, g, and h using only a ROM. ; g : Specify the ROM size (the number of words and the number of bits per word): . Y: ' Give the ROM truth table and draw the corresponding ROM programming. Problem 5.2 Design and draw a 1-to-8 demultiplexer using a 2—to-4 decoder with enable, a 1—to-2 decoder with enable, and a 1-to-4 demultiplexer. Use as few additional gates as possible. Clearly label each component’s inputs and outputs and the components themselves. Problem 5.3 In the following designs, the multiplexer data inputs should use the "obvious" selection codes: e.g., use 000 for D0, 001 for D1, 010 for D2, etc. Clear/y label each component’s inputs and outputs and the components themselves. a. Implement an 8:1 multiplexer using a 3:8 decoder, four 2:1 multiplexers with enable, and one additional gate. TN .. . ,. . D3 ‘ : 5 613.: i‘ 31"; C3179? ; z: i ;’ :-z-e:e»iiu15:¢;- ' ' ’ 5?. 5| b. Implement a quad 9:1 multiplexer using only four 8:1 multiplexers and one quad 2:1 multiplexer. Note: A quad n21 multiplexer is a single chip with four n:1 multiplexers, all having the same select inputs. 37"??? 2'? f.“ if; :93 ‘ a V 1 ;;§¢§§;flgz(s gags ;i~ ‘52:- ' 379.; .:$.ék¢flfi@fiijiiii ‘1 = , - Problem 5.4 In this problem you will implement a 15:1 multiplexer in two different ways. The multiplexer data inputs use selection codes 0000, 0001, ..., 1110 in the normal order (i.e., 0000 for Do, 0001 for D1, etc.). The implementation will consist of two 8:1 multiplexers and as few additional gates as possible. Clear/y label each component’s inputs and outputs and the components themselves. a. Let data inputs Do, ..., D7 feed (in order) into the data inputs of the first multiplexer. Let the output of the first MUX feed into the 000 input of the second MUX. Let data inputs D8, ..., D14 feed (in order) into the data inputs 001, 010, ..., 111 of the second MUX. Draw the implementation, using as few additional gates as possible. ",2 Problem 5.4 (continued) Clearly label each component’s inputs and outputs and the components themselves. b. Modify the implementation from part (a) so as to make the implementation even simpler. I.e., decide how to feed in the D and interconnect the multiplexers. Your circuit should use at most 4 gates (one of which is an inverter) in addition to the two 8:1 multiplexers. i mule: ‘ it; ' ' ‘ ...
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This note was uploaded on 06/21/2011 for the course ECE 290 taught by Professor Staff during the Spring '08 term at University of Illinois, Urbana Champaign.

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hwk05_s07_soln - 3;; an a i 3:3: i?" riot stapled...

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