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hwk07_s07_soln

# hwk07_s07_soln - penaity it" not staples ‘ Section 1...

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Unformatted text preview: penaity it" not staples? ‘ Section: 1 ‘3, . I: ) Score: Name: 5 . ' " Homework Set 7 ©D. J. Brown & C. N. Hadjicostis Due Wednesday, March 7, 2007 at 3pm Problem 7.0 Do Week #7 Mallard quizzes due 3 pm Tuesday. Problem 7. 1 Complete the timing diagram below, illustrating the behavior of an SR circuit, for different clocking: - positive-edge-triggered - negative-edge-triggered - master-slave - clocked latch (i.e., a latch with the simple clock/control input). In each case, assume the output Q is initially 0. Hint: Each of your waveforms should be (slightly) different. Problem 7.2 An AB flip—ﬂop is defined to operate as follows: AB=00 resets the flip—ﬂop to 0, AB=11 sets the flip—ﬂop to 1, and when AB = 01 or 10 the flip-ﬂop stays in the same state. a. Use an AB flip-ﬂop to build 3 JK flip-flop, using as few gates as possible. Specify appropriate boolean functions and draw the network. Show/explain how you derived your expressions. b. Repeat part (a) in order to build an AB flip- flop using a JK flip- ﬂop. 5 III - M {I We IIII @ New 3,30% 333+ ‘s+3+3 MA _ 33333333 33333 3, +33 M33433, 3 w #01 4S ‘0 931+ +3; 33+ +3 +33 ”i§§'§i?iiiii?,§2jfi‘ 453 W3_<_Ncu+ wrf‘e, 1+ ‘ .3333 +333 A8 3333533; ‘ : A 1 :: 51\$ 3] g ‘1 i‘ +3313 +3 {2+1 n3: +3333 if , 1 ,, ,, 5:: :;.:.;;:.;:':‘: ; " ' )as{" li'bow (Jam/3A6, as] +333, Mscnﬂ mfaf—s , 333,333+? 3553133333 usﬁm3m+sﬁ¥3 ii g 5 3 :.g _ ‘ , +334, “3,333, 91‘“ j§j§ : Problem 7.3 The sequential circuit below has a positive-edge-triggered T flip-ﬂop and a combinationai circuit G whose output is the function g(x,Q). CLGCK ' Complete the following timing diagram by showing the waveform for 9, assuming that the delay in G is negligible. 1 :: 3:1"7; nay-ind: ‘21 , ,3 . Ljdccgae ‘1 Problem 7.4 Consider the following logic diagram of a D flip-flop. a. Complete the timing diagram given below: show the waveforms for Q and I' o for w, x, y, and 2. Assume Q = 1 initially. Assume the gate delays are small (but d-l how the dela s an the diagram). Extra space is provided below for you to draw waveforms for w, X, y, and z. Problem 7.4 (continued) b. Add asynchronous PRE' ("preset") and CLR' ("clear") inputs to the copy of the circuit shown below. The circuit operation should be as follows: - When PRE' = 0 and CLR' = 1, then the outputs should be Q = 1 and Q‘ = O. I.e., PRE‘ = 0 sets the flip—flop state to 1. - When PRE' = 1 and CLR' = 0, then the outputs should be Q = O and Q' = 1. I.e., CLR' = 0 resets the flip—flop state to 0. Note that the preset and clear are "active low", i.e., active when their value is 0. (That is why the input names are complemented.) Correct behavior requires that clear and preset are not both 0 at the same time. Asynchronous means that the the effect of a low signal on either the clear or preset input is immediate. For instance, if CLR' = 0, then the flip-flop goes to state Q = 0 immediately, regardless of the value of the clock signal. Hint 1: Feed PRE' and CLR' as inputs to the NAND gates (replacing 2-input NANDs by 3-input NANDs). Hint 2: You will need to make PRE' an input to more than one NAND gate for the circuit to work correctly. The same is true for the CLR' input. Can you figure out why? c. In practice, it is often preferable to clear the flip—flops on the active edge of the clock: this is a synchronous clear. Design a D flip-ﬂop with a synchronous CLR' input. The flip-ﬂop should operate normally when the clear input (CLR') is equal to 1, but if CLR' goes to 0 then, on the next positive edge of the clock, the flip-ﬂop will be cleared to O. Hint 1: Represent the entire D circuit given above by a "box" and add a CLR' input with appropriate (external) gating. I.e., you do not need to modify the "insides" of the D circuit. Hint 2: Your answer will be a very simple circuit! ...
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