hwk08_s07_soln

# hwk08_s07_soln - penaity if not satame Score: Name: ,, ' f...

This preview shows pages 1–8. Sign up to view the full content.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: penaity if not satame Score: Name: ,, ' f Section: Homework Set 8 ©D. J. Brown & C. N. Hadjicostis Due Wednesday, March 14, 2007 at 3pm Problem 8.0 Do Week #8 Mallard quizzes due 3 pm Tuesday. Problem 8. 1 A sequential circuit has two inputs (X and Y) and one output (Z). The circuit is implemented using two D flip-ﬂops A and B (with inputs DA and DB, and outputs QA and Q5, respectively). The following Boolean equations describe the combinational logic that is used: DA = X'QA + XY DB = XIQA+XQB Z = XQB a. Draw the circuit. Problem 8.1 (continued) b. Give the next-state table, including columns for current state, inputs, output, D flip-ﬂop inputs, and next state. 2 ' i t c. Draw the state diagram. Nate: iii/335; oesign has two inputs; therefore, when iabeiing arrows foiiow the convention XWZ. Problem 8.2 In this problem you will implement a sequential circuit which "recognizes" all occurrences of the following sequences: 1100 and 1001. The output is 1 precisely when the last bit of either input sequence is read. Sample input: 0 O 1 O 1 1 1 1 1 0 0 Sample output: 0 O i. 0 O 0 1 011 001101... 000 000000... a. Draw a state diagram for this circuit, using as few states as possible. Be sure to give the meaning of each state. b. What is the minimum number of ﬂip—flops needed ~-f ‘ ' i ' in order to implement your circuit from part (a)? Problem 8.3 Recall the 101 sequence recognizer designed and implemented in lecture: a=00 b=01 C=11 - D1 = X'Ql'Qo Flg' 1 D0 = X + Q1'Qo Z = XQ1 Fig. 2 CLK a. Analyze the circuit in Fig. 2 in order to derive its state diagram. Retain the state names 00, 01, 10, 11 (i.e., avoid any state assignment). gaggestion: ﬁtart drawing the state diagram immediately. Start egg. if? state QIngOO and trace through the circuit in order t0 determine the next state (both for x: Q and for x m 1). Repeat for each state. b. Compare the state diagram in Fig. 1 with the state diagram you derived in part (a). In words, compare the number of states, the complexity of the circuit, and the functionality. Problem 8.4 Design a serial addition circuit. The circuit receives as input, one bit at a time, two unsigned n—bit integers A = an-1...a1ao and B = bn-1...b1bo. The output should be the sum S = A + B, where S = sn_1...slso. Assume that A and B are supplied with their least significant bits first: a0, be first, then a1, b1, and so on. a. Give the state diagram. Use as few states as possible and give the meaning of each state. ‘ ' " Problem 8.5 The state diagram shown below represents a network in which the output sequence 2 is equal to the input sequence x divided by 3. 0m U0 0m 1” A: remainder = 0 e B: remainder = 1 111 on C. remainder _ 2 a. Implement this network using the state assignment (QiQo): A=11, B=10, C=00. (i) Give the next-state table, complete with columns for current state, input, output, next state, and excitation inputs for two D ﬂip—ﬂops (see part ii) and two JK ﬂip-flops (see part iii). Problem 8.5 (part a, continued) (iii)Draw an implementation using two JK flip-ﬂops and a ROM; the ROM should replace all combinational circuitry. In this part, don’t show the contents of the ROM, just draw the ROM as a box, label its inputs and outputs, and give the box the name “ROM.” Problem 8.5 (continued) b. For the input x shown in the timing diagram below, give the corresponding 2 output and indicate the state of the machine during each clock period. Assume that the machine is initially in state A and that gate delays are negligible. c. Referring to the above timing diagram, give the input sequence x and the output sequence 2. » Give the decimal values of x and of z. d. Calculate x divided by 3 in binary; i.e., use long division to calculate x/ 112. List the sequence of remainders (e.g. 1,0,2,2,1,0); relate this sequence to the timing diagram information determined ...
View Full Document

## This note was uploaded on 06/21/2011 for the course ECE 290 taught by Professor Staff during the Spring '08 term at University of Illinois, Urbana Champaign.

### Page1 / 8

hwk08_s07_soln - penaity if not satame Score: Name: ,, ' f...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online