Unformatted text preview: Mallard ECE 290: Computer Engineering I  Spring 2007  Graded WebQuiz : Sequential... Page 1 of 5 Graded
Graded WebQuiz : Sequential Design: Even/Odd
Circuit
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Word Description
Design a 2state sequential network with a single input x and a single output z, which outputs:
1 if the number of 0's read thus far is even, and
0 if the number of 0's read thus far is odd
State Diagram
You may wish to first draw a state diagram.
State Table
Complete the nextstate table. There are 2 states, A and B. Before filling in the table, be sure you have
clearly in mind the meaning of each state. What is it we need to "remember"? The only past history
important to us is whether the total number of 0's read thus far is even or odd. Hence, we will have 2
states:
A: the number of 0's read thus far is even.
B: the number of 0's read thus far is odd.
Which state is the start state? A
Current State Input (x) Next State Output (z)
A 0 B 0 A 1 A 1 B 0 A 1 B 1 B 0 State
State Assignment
There are 2 states, and so a single flipflop is needed. Accordingly, there will be a single state variable
Q. We arbitrarily choose the following state assignment:
A = 0, B = 1 https://mallard.cites.uiuc.edu/ECE290/webgrade.cgi?SessionID=mding3_1070311_13325... 3/11/2007 Mallard ECE 290: Computer Engineering I  Spring 2007  Graded WebQuiz : Sequential... Page 2 of 5 Complete the state table below, using the above state assignment.
Current
Current State Input Next State Output Q x Q+ z 0 0 1 0 0 1 0 1 1 0 0 1 1 1 1 0 Your points: 100.00
Determine
Determine the Output Functions
Q'x+Qx'
z(Q,x) = Q'x+Qx' Enter a minimal SOP Boolean expression
FlipFlipDecide Type(s) of FlipFlops to Use and Determine FlipFlop Excitation Functions
To implement this network we need a single flipflop: D, T, JK, or SR. In this exercise we will get lots
of practice and implement the network 4 separate times. Determine equations for the flipflop inputs.
When completing the state tables, be sure to use don't cares wherever possible.
FlipOption 1: A D FlipFlop Implementation
Give a D flipflop implementation, by providing the excitation input values in the table and then giving
a minimal SOP expression for D.
Current
Current
State Input FF
Excitation Q x D 0 0 1 0 1 0 1 0 0 1 1 1 D(Q,x) Q'x'+Qx
D(Q,x) = Q'x'+Qx Enter a minimal SOP Boolean
expression Your points: 100.00
FlipOption 2: A JK FlipFlop Implementation
Give a JK flipflop implementation, by providing the excitation input values in the table and then
giving minimal SOP expressions for J and for K. https://mallard.cites.uiuc.edu/ECE290/webgrade.cgi?SessionID=mding3_1070311_13325... 3/11/2007 Mallard ECE 290: Computer Engineering I  Spring 2007  Graded WebQuiz : Sequential... Page 3 of 5 Current
Current State Input FF Excitation Q x J K 0 0 1 X 0 1 0 X 1 0 X 1 1 1 X 0 J(Q,x) x
J(Q,x) = x'' Enter a minimal SOP Boolean expression
K(Q,x) = x'' Enter a minimal SOP Boolean expression
K(Q,x) x Your points: 100.00
Option
FlipOption 3: A T FlipFlop Implementation
Give a T flipflop implementation, by providing the excitation input values in the table and then giving
a minimal SOP expression for T.
Current
Current State Input FF Excitation Q x T 0 0 1 0 1 0 1 0 1 1 1 0 T(Q,x) x
T(Q,x) = x'' Enter a minimal SOP Boolean expression Your points: 100.00
FlipOption 4: An SR FlipFlop Implementation
Give an SR flipflop implementation, by providing the excitation input values in the table and then
giving minimal SOP expressions for S and for R. Current
Current
State Input Q x 0 0 1 0 0 1 0 X 1 0 0 1 1 1 X 0 FF Excitation
S R
S(Q,x) Q'x'
S(Q,x) = Q'x' Enter a minimal SOP Boolean expression
Qx'
R(Q,x) = Qx' Enter a minimal SOP Boolean expression https://mallard.cites.uiuc.edu/ECE290/webgrade.cgi?SessionID=mding3_1070311_13325... 3/11/2007 Mallard ECE 290: Computer Engineering I  Spring 2007  Graded WebQuiz : Sequential... Page 4 of 5 Your points: 100.00
Implement the Circuit
We have already determined the output and the FF excitation functions. A combinational circuit
suffices to implement these.
Suppose we decide to implement our network using a D flipflop and that the combinational circuitry to
compute D and z uses only AND, OR, and NOT gates. Consider only 2level ANDOR
implementations, corresponding to the equations we derived above.
How many AND and OR gates (total) are needed to compute the FF input D and the output z? 6 How many INVERTERS are needed? 1 Note: The state variable Q is available in both complemented and uncomplemented form (because flipflops provide Q' along with Q), but in general the input x is not available already complemented.
Suppose instead that we decide to implement our network using a JK flipflop.
How many AND and OR gates (total) are needed to compute the FF inputs J and K and the
output z? 3
How many INVERTERS are needed? 1
Draw a circuit to implement the functions determined here. (E.g. try using a D flipflop and an XOR
gate.) Study this circuit. When the input x changes, what other circuit values can change immediately?
What changes will need to wait for the clock pulse? Be sure you understand sequential network timing!
Item 10: You have filled in all 8 entries in the table correctly.
Item 12: You have filled in all 4 entries in the table correctly.
Item 14: You have filled in all 8 entries in the table correctly.
Item 17: You have filled in all 4 entries in the table correctly.
Item 19: You have filled in all 8 entries in the table correctly.
You received a raw score of 100% on this question. WebQuiz
WebQuiz Grade Summary
Raw score
Adjusted score
Minimum passing score
Grade for this submission
Cumulative Grade
Cumulative 100.00%
100.00%
60.00%
100% 100% https://mallard.cites.uiuc.edu/ECE290/webgrade.cgi?SessionID=mding3_1070311_13325... 3/11/2007 Mallard ECE 290: Computer Engineering I  Spring 2007  Graded WebQuiz : Sequential... Page 5 of 5 NEW Quiz Mallard Copyright © 19952000
Course Content Copyright?19952007 Donna J. Brown. All rights reserved. https://mallard.cites.uiuc.edu/ECE290/webgrade.cgi?SessionID=mding3_1070311_13325... 3/11/2007 ...
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 Electrical Engineering, Nondeterministic finite state machine, State transition table

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