Written Problem Set #9 - Mallard ECE 290: Computer...

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Mallard ECE 290: Computer Engineering I - Spring 2007 - Written Prob. .. https://mallard.cites.uiuc.edu/ECE290/material.cgi?SessionID=mding3_. .. 1 of 3 4/29/2007 4:26 PM Written Problem Set #9 ECE 290 Problem Set #9 Due: March 28, 2007 Problem 9.0 Do Week #9 Mallard quizzes due Tuesday, March 27. New Instructions for this Written Problem Set : Worksheets are provided for Problems 9.3 and 9.5. These problems must be completed on these worksheets. All other problems are to be completed on your own paper, subject to the following restriction: All problems are to be completed on separate sheets of paper . Individual problems may span multiple sheets of paper, but not two problems should appear on the same sheet of paper. Problem 9.1 Consider the 3-bit counter built with 3 T flip-flops whose inputs are T 2 = Q 2 'Q 1 + Q 0 T 1 = Q 2 'Q 1 ' + Q 2 Q 1 T 0 = Q 2 Q 1 ' Draw the state diagram for this circuit (include all don't care states). In what Q 2 Q 1 Q 0 sequence does this counter count? Assume the (correct) count sequence starts in state 000. a. Explain why this circuit is not self-correcting. b. Make a small modification to T 1 (add one literal to the original expression) so that the resulting circuit is self-correcting. Specify this modified T 1 in minimal SOP form and show the new state diagram. Do not modify the (correct/normal) count sequence. c. Problem 9.2 Implement a 4-bit register with load and increment operations (in other words, a 4-bit counter with parallel load). Your register should have control inputs LOAD and COUNT, data inputs D3, D2, D1, D0, as well as a clock input. The outputs are Q3, Q2, Q1, Q0, and CO (output carry). The LOAD and COUNT inputs operate as follows:
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Written Problem Set #9 - Mallard ECE 290: Computer...

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