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Unformatted text preview: Mallard ECE 290: Computer Engineering I - Spring 2007 - HWK #10 So... https://mallard.cites.uiuc.edu/ECE290/material.cgi?SessionID=mding3_... 1 of 5 4/14/2007 12:32 PM HWK #10 Solutions Problem 10.1. Problem 10.2. Problem 10.3. Mallard ECE 290: Computer Engineering I - Spring 2007 - HWK #10 So... https://mallard.cites.uiuc.edu/ECE290/material.cgi?SessionID=mding3_... 2 of 5 4/14/2007 12:32 PM Problem 10.4. Problem 10.5. (a) Assume Z=0 in all states where it is not explicitly defined as 1. The table may seem confusing at first. Each column of the table is separated by an active edge of the clock. Therefore, in the first column, we are in state ST1; regardless of the input in ST1 we output 0. When the next active edge of the clock is encountered, we proceed to the next state according to the signals ABC. Since A=0, we proceed to state ST1; therefore we indicate state ST1 in the second column. Again, the output is 0 regardless of the inputs. However, our inputs have changed: now A=1. Therefore, when thecolumn....
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This note was uploaded on 06/21/2011 for the course ECE 290 taught by Professor Staff during the Spring '08 term at University of Illinois, Urbana Champaign.
- Spring '08