Register Transfer - .. 2 of 2 3/31/2007 8:18 PM (b) For the...

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Mallard ECE 290: Computer Engineering I - Spring 2007 - Graded Web. .. https://mallard.cites.uiuc.edu/ECE290/webgrade.cgi?SessionID=mding3. .. 1 of 2 3/31/2007 8:18 PM Graded WebQuiz: Register Transfer You have submitted this WebQuiz 2 times (including this time). You may submit this WebQuiz a total of 10 times and receive full credit. Please be sure you can implement all details of a 2-bit bus transfer with 8 registers. Draw the implementation - without looking at any existing figures. Question #1 Consider the bus system shown below, with four n-bit registers R0, R1, R2, and R3. Let D1 and D0 be the input variables to the decoder, and S1 and S0 the select inputs for the multiplexer. (a) For D1D0S1S0 = 0110, the source register is R2 and the destination register is R1 .
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Mallard ECE 290: Computer Engineering I - Spring 2007 - Graded Web. .. https://mallard.cites.uiuc.edu/ECE290/webgrade.cgi?SessionID=mding3.
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Unformatted text preview: .. 2 of 2 3/31/2007 8:18 PM (b) For the register transfer R0 <-- R3, give the 4-bit coding: D1D0S1S0 = 0011 . You received a raw score of 100% on this question. Question #2 Consider the design of a 16-bit bus transfer system with 128 registers (each with 16 bits) and a single bus. What is the size of the destination decoder? 7 -to- 128 How many multiplexers (with a single output) do we need? 16 What is the size of each of these multiplexers? 128 -to- 1 You received a raw score of 100% on this question. WebQuiz Grade Summary Raw score 100.00% Adjusted score 100.00% Minimum passing score 60.00% Grade for this submission 100% Cumulative Grade 100% To improve a grade, you must load a new quiz: NEW Quiz Mallard Copyright 1995-2000 Course Content Copyright 1995-2007 Donna J. Brown. All rights reserved....
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This note was uploaded on 06/21/2011 for the course ECE 290 taught by Professor Staff during the Spring '08 term at University of Illinois, Urbana Champaign.

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Register Transfer - .. 2 of 2 3/31/2007 8:18 PM (b) For the...

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