The LC-3 ISA
needed to execute the instruction. The speciﬁc operation of each LC-3
instruction is described in Section A.3.
Illegal opcode exception
1101 has not been speciﬁed. If an
instruction contains 1101 in bits [15:12], an illegal opcode exception
occurs. Section A.4 explains what happens.
A 16-bit register containing the address of the next
instruction to be processed.
General purpose registers
Eight 16-bit registers, numbered from 000 to
Three 1-bit registers: N (negative), Z (zero), and P
(positive). Load instructions (LD, LDI, LDR, and LEA) and operate
instructions (ADD, AND, and NOT) each load a result into one of the eight
general purpose registers. The condition codes are set, based on whether
that result, taken as a 16-bit 2’s complement integer, is negative
, or positive
All other LC-3 instructions leave the condition codes unchanged.
Input and output are handled by load/store
(LDI/STI, LDR/STR) instructions using memory addresses to designate
each I/O device register. Addresses xFE00 through xFFFF have been
allocated to represent the addresses of I/O devices. See Figure A.1. Also,
Table A.3 lists each of the relevant device registers that have been identiﬁed
for the LC-3 thus far, along with their corresponding assigned addresses
from the memory address space.
I/O devices have the capability of interrupting the
processor. Section A.4 describes the mechanism.
The LC-3 supports eight levels of priority. Priority level 7
(PL7) is the highest; PL0 is the lowest. The priority level of the currently
executing process is speciﬁed in bits PSR[10:8].
Processor status register (PSR)
A 16-bit register, containing status
information about the currently executing process. Seven bits of the PSR
have been deﬁned thus far. PSR speciﬁes the privilege mode of
the executing process. PSR[10:8] speciﬁes the priority level of the currently
executing process. PSR[2:0] contains the condition codes. PSR is N,
PSR is Z, and PSR is P.