lc3_c - appendix c The Microarchitecture of the LC-3 We...

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“app-c” — 2003/6/30 — page 565 — #1 appendix c The Microarchitecture of the LC-3 We have seen in Chapters 4 and 5 the several stages of the instruction cycle that must occur in order for the computer to process each instruction. If a microar- chitecture is to implement an ISA, it must be able to carry out this instruction cycle for every instruction in the ISA. This appendix illustrates one example of a microarchitecture that can do that for the LC-3 ISA. Many of the details of the microarchitecture and the reasons for each design decision are well beyond the scope of an introductory course. However, for those who want to understand how a microarchitecture can carry out the requirements of each instruction of the LC-3 ISA, this appendix is provided. C.1 Overview Figure C.1 shows the two main components of an ISA: the data path , which contains all the components that actually process the instructions, and the control , which contains all the components that generate the set of control signals that are needed to control the processing at each instant of time. We say, “at each instant of time,” but we really mean during each clock cycle . That is, time is divided into clock cycles . The cycle time of a microprocessor is the duration of a clock cycle. A common cycle time for a microprocessor today is 0.5 nanoseconds, which corresponds to 2 billion clock cycles each second. We say that such a microprocessor is operating at a frequency of 2 gigahertz. At each instant of time—or, rather, during each clock cycle—the 49 control signals (as shown in Figure C.1) control both the processing in the data path and the generation of the control signals for the next clock cycle. Processing in the data path is controlled by 39 bits, and the generation of the control signals for the next clock cycle is controlled by 10 bits. Note that the hardware that determines which control signals are needed each clock cycle does not operate in a vacuum. On the contrary, the control signals needed in the “next” clock cycle depend on all of the following: 1. What is going on in the current clock cycle. 2. The LC-3 instruction that is being executed. 3. The privilege mode of the program that is executing. 4. If that LC-3 instruction is a BR, whether the conditions for the branch have been met (i.e., the state of the relevant condition codes).
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“app-c” — 2003/6/30 — page 566 — #2 566 appendix c The Microarchitecture of the LC-3 39 37 R Control 10 INT Control Signals PSR[15] IR[15:11] BEN (J, COND, IRD) Memory, I/O Addr 16 Data, Inst. 16 16 Data Data Path 2 49 Figure C.1 Microarchitecture of the LC-3, major components 5. Whether or not an external device is requesting that the processor be interrupted. 6. If a memory operation is in progress, whether it is completing during this cycle.
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This note was uploaded on 06/21/2011 for the course ECE 290 taught by Professor Staff during the Spring '08 term at University of Illinois, Urbana Champaign.

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lc3_c - appendix c The Microarchitecture of the LC-3 We...

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