ECE 290 LAB#3 - Mallard ECE 290 Computer Engineering I Spring 2007 ECE 290 L https/mallard.cites.uiuc.edu/ECE290/material.cgi?SessionID=mding3 1 of

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Unformatted text preview: Mallard ECE 290: Computer Engineering I - Spring 2007 - ECE 290: L... https://mallard.cites.uiuc.edu/ECE290/material.cgi?SessionID=mding3_... 1 of 9 4/20/2007 3:58 AM ECE 290: LAB #3 (due Feb 22, 3 pm) LAB 3: All About Adders Introduction As you look through this lab, you will notice that it is composed of the following sections: Setup 1. Full Adder 2. Ripple Adder 3. Carry Lookahead Adder 4. Sections one, two, and three are intended to teach you a few new features of HDL Designer and to give you some practice creating circuits on your own. Section 4 is intended to teach you everything you need to know about carry lookahead adders. It is particularly important that you take the time to read and understand the descriptions of the theory behind carry lookahead adders; answering the questions will be much simpler if you do. The lab is long, but take heart: after completing it, you will be a carry lookahead adder expert. When you finish the lab, you should turn in the following items for a grade ( stapled in this order): A Sheet Plot of the single bit full adder cell and the simulation waveform. A Sheet Plot of the 4-bit adder circuit and the simulation waveform showing correct operation of the 4-bit adder. A Sheet Plot of the completed CLAlogic and CLA4bit modules, as well as a simulation waveform showing correct execution of the 'cla4.do' file. A Sheet Plot of the completed CLA16bit module, as well as a simulation waveform showing correct execution of the 'cla16.do' file. The Lab #3 worksheet. Note: the questions on this worksheet will be worth most of the credit for the lab. Be sure to include your name on each page. Good luck, and as always, let us know if you have questions. 1. Setting up the Lab 1.1 Component Delays A crucial part of this lab is the consideration of component delays. So far, we have been using ideal components with no gate delays. With an ideal gate, we neglect the time required for the output of the gate to change from low to high (rise time) or to change from high to low (fall time). However, actual gates cannot change output values instantaneously, thus imposing a limit on the number of computations per unit time a gate can perform. The numbers near the gate outputs in Figure 1 represent the rise and fall times of each gate. You won't worry have to worry about setting the delay yourself since the gates that we'll be using will have the proper delays set. 1.2 Library Mapping Start out by adding a directory called lab3 in your ece290 directory. Then open HDLDesigner and create a library mapping called LAB3 that uses the lab3 folder that you just created as its root (see lab 2 if you don't remember how to set up a library mapping). For this lab, you'll need to use some gates that have a delay - there are none readily available in HDLDesigner's libraries, so you'll have to download the files for these gates. The files are stored in a "tar" file, which is an archive in UNIX, and this archive has been compressed into a .gz file (a type of 'zipped' file). To get the file, follow these steps:file, which is an archive in UNIX, and this archive has been compressed into a ....
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This note was uploaded on 06/21/2011 for the course ECE 290 taught by Professor Staff during the Spring '08 term at University of Illinois, Urbana Champaign.

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ECE 290 LAB#3 - Mallard ECE 290 Computer Engineering I Spring 2007 ECE 290 L https/mallard.cites.uiuc.edu/ECE290/material.cgi?SessionID=mding3 1 of

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